參數(shù)資料
型號(hào)： MAX1403EAI+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 34/36頁(yè)
文件大小： 0K
描述： IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 18
采樣率（每秒）： 480
數(shù)據(jù)接口： QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21.45mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 3 個(gè)差分，單極；3 個(gè)差分，雙極；5 個(gè)偽差分，單極；5 個(gè)偽差分，雙極
0
100
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________________________________________________________________________________
7
TIMING CHARACTERISTICS
(V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, AGND = DGND, fCLKIN = 2.4576MHz, input logic 0 = 0V, logic 1 = VDD, TA = TMIN to
TMAX, unless otherwise noted.) (Notes 20, 21, 22)
Bus Relinquish Time After SCLK
Rising Edge (Note 27)
t10
ns
SCLK Falling Edge to Data Valid
Delay (Notes 25, 26)
t6
0
100
ns
INT High Time
tINT
560 / N
tCLKIN
ns
X2CLK = 1, N = 2(2 MF1 + MF0)
Crystal oscillator or clock exter-
nally supplied for specified perfor-
mance (Notes 23, 24)
SCLK Setup to Falling Edge CS
t4
30
ns
SCLK Low Pulse Width
t8
100
ns
10
100
SCLK Rising Edge to INT High
(Note 28)
t11
200
CS Rising Edge to SCLK Rising
Edge Hold Time (Note 22)
t9
0
ns
SCLK High Pulse Width
t7
100
ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t5
30
ns
280 / N
tCLKIN
INT to CS Setup Time (Note 9)
t3
X2CLK = 0, N = 2(2 MF1 + MF0)
0
ns
RESET Pulse Width Low
t2
100
ns
Master Clock Input Low Time
fCLKIN LO
0.4
tCLKIN
ns
tCLKIN = 1 / fCLKIN, X2CLK = 0
Master Clock Input High Time
fCLKIN HI
0.4
tCLKIN
ns
tCLKIN = 1 / fCLKIN, X2CLK = 0
Master Clock Frequency
fCLKIN
0.8
5.0
MHz
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
0.4
2.5
CONDITIONS
ns
X2CLK = 0
X2CLK = 1
Note 16: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate
correctly.
Note 17: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 18: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 19: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
When used with a resonator or crystal between CLKIN and CLKOUT, the actual power dissipation and IDD in standby
mode will depend on the resonator or crystal type.
30
ns
t12
SCLK Setup to Falling Edge CS
SERIAL-INTERFACE READ OPERATION
SERIAL-INTERFACE WRITE OPERATION
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