參數資料
型號: MAX1403EAI+T
廠商: Maxim Integrated Products
文件頁數: 18/36頁
文件大?。?/td> 0K
描述: IC ADC 18BIT LP 28-SSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
位數: 18
采樣率(每秒): 480
數據接口: QSPI?,串行,SPI?
轉換器數目: 1
功率耗散(最大): 21.45mW
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數目和類型: 3 個差分,單極;3 個差分,雙極;5 個偽差分,單極;5 個偽差分,雙極
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________
25
Table 14. REXT, CEXT Values for Less than 16-Bit Gain Error in Buffered (BUFF = 1)
Mode—All Modulator Sampling Frequencies (MF1, MF0 = XX); X2CLK = 0; CLKIN =
2.4576MHz
10
2
10
4
1
CEXT = 0pF
CEXT = 50pF
CEXT = 100pF
10
PGA GAIN
10
CEXT = 500pF
CEXT = 1000pF
CEXT = 5000pF
EXTERNAL RESISTANCE, REXT (k
)
10
16
10
32
8
10
64
10
128
10
Reference Input
The MAX1403 is optimized for ratiometric measure-
ments and includes a fully differential reference input.
Apply the reference voltage across REFIN+ and REFIN-,
ensuring that REFIN+ is more positive than REFIN-.
REFIN+ and REFIN- must be between AGND and V+.
The MAX1403 is specified with a +1.25V reference.
Modulator
The MAX1403 performs analog-to-digital conversion
using a single-bit, second-order, switched-capacitor
modulator. A single comparator within the modulator
quantizes the input signal at a much higher sample rate
than the bandwidth of the signal to be converted. The
quantizer then presents a stream of 1s and 0s to the
digital filter for processing, to remove the frequency-
shaped quantization noise.
The MAX1403 modulator provides 2nd-order frequency
shaping of the quantization noise resulting from the sin-
gle bit quantizer. The modulator is fully differential for
maximum signal-to-noise ratio and minimum suscepti-
bility to power-supply noise.
The modulator operates at one of a total of eight differ-
ent sampling rates (fM) determined by the master clock
frequency (fCLKIN), the X2CLK bit, the CLK bit, and the
modulator frequency control bits MF1 and MF0. Power
dissipation is optimized for each of these modes by
controlling the bias level of the modulator. Table 15
shows the input and reference sample rates.
PGA
A programmable gain amplifier (PGA) with a user-
selectable gain of x1, x2, x4, x8, x16, x32, x64, or x128
(Table 6) precedes the modulator. Figure 8 shows the
default bipolar transfer function with the following illus-
trated codes: 1) PGA = 0, DAC = 0; 2) PGA = 3, DAC =
0; or 3) PGA = 3, DAC = 3.
Output Noise
Tables 16a and 16b show the rms noise for typical out-
put frequencies (notches) and -3dB frequencies for the
MAX1403 with fCLKIN = 2.4576MHz. The numbers
given are for the bipolar input ranges with VREF =
+1.25V, with no buffer (BUFF = 0), and with the buffer
inserted (BUFF = 1). These numbers are typical and
are generated at a differential analog input voltage of 0.
Figure 7 shows graphs of Effective Resolution vs. Gain
and Notch Frequency. The effective resolution values
were derived from the following equation:
Effective Resolution = (SNRdB - 1.76dB) / 6.02
The maximum possible signal divided by the noise of
the device, SNRdB, is defined as the ratio of the input
full-scale voltage (i.e., 2 VREFIN / GAIN) to the output
rms noise. Note that it is not calculated using peak-to-
peak output noise numbers. Peak-to-peak noise num-
bers can be up to 6.6 times the rms numbers, while
effective resolution numbers based on peak-to-peak
noise can be 2.5 bits below the effective resolution
based on rms noise, as quoted in the tables.
The noise shown in Tables 16a and 16b is composed
of device noise and quantization noise. The device
noise is relatively low, but becomes the limiting noise
source for high gain settings. The quantization noise is
dependent on the notch frequency and becomes the
dominant noise source as the notch frequency is
increased.
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