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| 型號： | MAX1329BETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 53/78頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 300KSPS 40-TQFN-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準包裝： | 2,500 |
| 系列： | * |
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MAX1329/MAX1330
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
57
APIO Control Register
The Analog Programmable Input/Output (APIO) Control
register configures the modes of APIO1–APIO4.
APIO1–APIO4 I/O logic levels are referenced to AVDD and
AGND (see Analog I/O in the
Electrical Characteristics
table). APIO_ is configurable as a general-purpose input,
active-low wake-up input, general-purpose output, or seri-
al-interface, level-shifted buffered I/O.
AP_MD<1:0>: APIO_ Mode Configuration bits (default
= 00). AP_MD<1:0> configures the APIO_ mode
according to Table 30.
MSB
LSB
NAME
AP4MD1
AP4MD0
AP3MD1
AP3MD0
AP2MD1
AP2MD0
AP1MD1
AP1MD0
DEFAULT
0000
Table 29. SPDT2 Switch Control Configuration
SPDT2 SWITCH STATE
SPDT21
BIT
SPDT20
BIT
DPIO4
DPIO3
DPIO2
DPIO1
SNO2-TO-SCM2 STATE
SNC2-TO-SCM2 STATE
0
Open
0
X
XXX1
Closed
0
X
1
X
Closed
0
X
1
X
Closed
0
X
1
X
Closed
0
1
X
Closed
1
0
Open
Closed
1
X
XXX1
Closed
Open
1
X
1
X
Closed
Open
1
X
1
X
Closed
Open
1
X
1
X
Closed
Open
1
X
Closed
Open
Table 30. APIO_ Mode Bit Configuration
AP_MD1
AP_MD0
MODE
DESCRIPTION
0
GPI
Digital input. APIO_ logic level read from AP_LL register bit.
0
1
WUL
Digital input. A falling edge on APIO_ sets the OSCE bit to 1 enabling the oscillator.
1
0
GPO
Digital output. Set the APIO_ logic level by writing to the AP_LL register bit.
1
SPI
Digital input or output. The SPI mode functions differ for each APIO1–APIO4.
APIO1 digital input. DOUT outputs the APIO1 logic level when CS is high, and
APIO1 is a GPI, when
CS is low. Set the resistor pullup configuration with the
AP1PU bit.
APIO2 digital output. APIO2 outputs the DIN logic level when CS is high and
becomes a GPO with the level set by AP2LL bit when
CS is low.
APIO3 digital output. APIO3 outputs the SCLK logic level when CS is high and
becomes a GPO with the level set by the AP3LL bit when
CS is low.
APIO4 digital output. APIO4 inverts and then outputs the CS logic level.
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| MAX132CNG+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit .1ksps .545V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX132CWG | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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