參數(shù)資料
型號(hào): MAX1329BETL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 17/78頁(yè)
文件大?。?/td> 0K
描述: IC DAS 12BIT 300KSPS 40-TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: *
MAX1329/MAX1330
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
24
______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1329
MAX1330
NAME
FUNCTION
24
OUTA
DACA Force-Sense Output. Also internally connected to ADC mux.
25
FBA
DACA Force-Sense Feedback Input. Also internally connected to ADC mux.
26
REFDAC
DAC Internal Reference Buffer Output/DAC External Reference Input. In internal reference
mode, REFDAC provides a 1.25V, 2.048V, or 2.5V internal reference buffer output. In
external DAC reference buffer mode, disable internal reference buffer. Bypass REFDAC to
AGND with a 1F capacitor.
27
SNC2
Analog Switch 2 Normally-Closed Terminal
28
SCM2
Analog Switch 2 Common Terminal
29
SNO2
Analog Switch 2 Normally-Open Terminal
30
AIN2
Analog Input 2. Also internally connected to ADC mux.
31
AIN1
Analog Input 1. Also internally connected to ADC mux.
32
REFADC
ADC Internal Reference Buffer Output/ADC External Reference Input. In internal reference
mode, REFADC provides a 1.25V, 2.048V, or 2.5V internal reference buffer output. In
external ADC reference buffer mode, disable internal reference buffer. Bypass REFADC to
AGND with a 1F capacitor.
33
REFADJ
Internal Reference Output/Reference Buffer Amplifiers Input. In internal reference mode,
bypass REFADJ to AGND with a 0.01F capacitor. In external reference mode, disable
internal reference.
34
AGND
Analog Ground
35
AVDD
Analog Supply Input. Bypass AVDD to AGND with at least a 0.01F capacitor. With the
charge pump enabled, see Table 32 for required capacitor values.
36
C1B
Charge-Pump Capacitor Input B. Connect CFLY across C1A and C1B. See Table 32 for
required capacitor values.
37
C1A
Charge-Pump Capacitor Input A. Connect CFLY across C1A and C1B. See Table 32 for
required capacitor values.
38
DVDD
Digital Supply Input. Bypass DVDD to DGND with at least a 0.01F capacitor. When using
charge pump, see Table 32 for required capacitor values.
39
DGND
Digital Ground
40
CLKIO
Clock Input/Output. In internal clock mode, enable CLKIO output for external use. In
external clock mode, apply a clock signal at CLKIO for the ADC and charge pump.
——
EP
Exposed Pad. The exposed pad is located on the package bottom and is internally
connected to AGND. Connect EP to the analog ground plane. Do not route any PCB traces
under the package.
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