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參數(shù)資料
| 型號： | MAX1324ECM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 8CH 2MSPS 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.82W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，雙極 |
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MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________
17
Data Throughput
The data throughput (fTH) of the MAX1316–MAX1318/
MAX1320–MAX1322/MAX1324–MAX1326 is a function
of the clock speed (fCLK). In internal-clock mode, fCLK =
10MHz. In external-clock mode, 100kHz ≤ fCLK ≤
12.5MHz. When reading during conversion (Figures 5
and 6), calculate fTH as follows:
where N is the number of active channels and tQUIET
includes acquistion time tACQ. tQUIET is the period of bus
inactivity before the rising edge of CONVST. Typically use
tQUIET = tACQ + 50ns, and prevent disturbance on the
output bus from corrupting signal acquistion. See the
Starting a Conversion section for more information.
Reading a Conversion Result
Reading During a Conversion
Figures 5 and 6 show the interface signals for initiating a
read operation during a conversion cycle. These figures
show two channels selected for conversion. If more chan-
nels are selected, the results are available successively
every third clock cycle. CS can be low at all times; it can
be low during the RD cycles, or it can be the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC to go low (about 1.6s in internal-clock
mode or 17 clock cycles in external-clock mode) before
reading the first conversion result. Read the conversion
result by bringing RD low, thus latching the data to the
parallel digital-output bus. Bring RD high to release the
digital bus. Wait for the next falling edge of EOC (about
300ns in internal-clock mode or three clock cycles in
external-clock mode) before reading the next result.
When the last result is available, EOLC goes low.
f
t
xN
f
TH
QUIET
CLK
=
+
+
1
16
3
1
()
Table 3. Throughput vs. Channels Sampled (tQUIET = tACQ = 200ns, fCLK = 10MHz)
CHANNELS
SAMPLED
(N)
CLOCK CYCLES
UNTIL LAST
RESULT
CLOCK CYCLE FOR
READING LAST
CONVERSION
TOTAL
CONVERSION
TIME (ns)
SAMPLES PER
SECOND
(ksps)
THROUGHPUT
PER CHANNEL
(ksps)
1
16
1
1900
526
2
19
1
2200
909
455
3
22
1
2500
1200
400
4
25
1
2800
1429
357
5
28
1
3100
1613
323
6
31
1
3400
1765
294
7
34
1
3700
1892
270
8
37
1
4000
2000
250
Figure 5. Read During Conversion—Two Channels Selected, Internal Clock
CONVST
CH0
TRACK
HOLD
D0–D13
SAMPLE
t1
t13
t12
t10
t3
t11
TRACK
CH1
tCONV
tNEXT
EOC
RD
t20
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