參數(shù)資料
型號(hào): MAX1324ECM+T
廠商: Maxim Integrated Products
文件頁數(shù): 23/27頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 8CH 2MSPS 48LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 2M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.82W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)單端,雙極
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
_______________________________________________________________________________________
5
Note 1:
For the MAX1316/MAX1317/MAX1318, VIN = 0 to +5V. For the MAX1320/MAX1321/MAX1322, VIN = -5V to +5V. For the
MAX1324/MAX1325/MAX1326, VIN = -10V to +10V.
Note 2:
All channel performance is guaranteed by correlation to a single channel test.
Note 3:
Offset nulled.
Note 4:
The analog input resistance is terminated to an internal bias point. Calculate the analog input current using:
for VCH within the input voltage range.
Note 5:
Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK = 10MHz). See the Data
Throughput section for more information.
Note 6:
All analog inputs are driven with an FS 100kHz sine wave.
I
VV
R
CH
BIAS
CH
_
=
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal clock
1.6
1.8
s
Time-to-First-Conversion Result
tCONV
External clock, Figure 6
16
Clock
cycles
Internal clock
0.3
0.36
s
Time-to-Next-Conversion Result
tNEXT
External clock, Figure 6
3
Clock
cycles
CONVST Pulse-Width Low
(Acquisition Time)
tACQ
(Note 9)
0.16
100
s
CS Pulse Width
t2
30
ns
RD Pulse-Width Low
t3
30
ns
RD Pulse-Width High
t4
30
ns
WR Pulse-Width Low
t5
30
ns
CS to WR
t6
(Note 10)
ns
WR to CS
t7
(Note 10)
ns
CS to RD
t8
(Note 10)
ns
RD to CS
t9
(Note 10)
ns
Data-Access Time
(RD Low to Valid Data)
t10
30
ns
Bus-Relinquish Time (RD High)
t11
30
ns
Internal clock
80
ns
EOC Pulse Width
t12
External clock, Figure 6
1
Clock
cycles
Input-Data Setup Time
t14
10
ns
Input-Data Hold Time
t15
10
ns
External-Clock Period
t16
0.08
10.00
s
External-Clock High Period
t17
Logic sensitive to rising edges
20
ns
External-Clock Low Period
t18
Logic sensitive to rising edges
20
ns
External-Clock Frequency
(Note 11)
0.1
12.5
MHz
Internal-Clock Frequency
10
MHz
CONVST High to CLK Edge
t19
20
(Note 12)
ns
EOC Low to RD
t20
0ns
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