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參數資料
| 型號： | MAX1324ECM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 6/27頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 8CH 2MSPS 48LQFP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 位數： | 14 |
| 采樣率（每秒）： | 2M |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 1.82W |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 8 個單端，雙極 |
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MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
14
______________________________________________________________________________________
To improve the input-signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance and settle
quickly. For example, the MAX4265 can be used for +5V
unipolar devices, or the MAX4350 can be used for ±5V
bipolar inputs.
The T/H aperture delay is typically 13ns. The aperture-
delay mismatch between T/Hs of 50ps allows the relative
phase information of up to eight different inputs to be
preserved. Figure 2 shows a simplified equivalent input
circuit, illustrating the ADC’s sampling architecture.
Input Bandwidth
The input tracking circuitry has a 12MHz small-signal
bandwidth, making it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Input Range and Protection
These devices provide ±10V, ±5V, or 0 to +5V analog
input voltage ranges. Figure 2 shows the equivalent input
circuit. Overvoltage protection circuitry at the analog
input provides ±16.5V fault protection for the bipolar input
devices and ±6.0V fault protection for the unipolar input
devices. This fault-protection circuit limits the current
going into or out of the device to less than 50mA, provid-
ing an added layer of protection from momentary over-
voltage or undervoltage conditions at the analog input.
Power-Saving Modes
Shutdown Mode
During shutdown, the analog and digital circuits in the
device power down and the device draws less than
100A from AVDD, and less than 100A from DVDD.
Select shutdown mode using the SHDN input. Set SHDN
high to enter shutdown mode. After coming out of shut-
down, allow a 1ms wake-up time before making the first
conversion. When using an external clock, apply at least
20 clock cycles with CONVST high before making the first
conversion. When using internal-clock mode, wait at least
2s before making the first conversion.
ALLON
ALLON is useful when some of the analog input channels
are selected (see the
Configuration Register section).
Drive ALLON high to power up all input channel circuits,
regardless of whether they are selected as active by the
configuration register. Drive ALLON low or connect to
ground to power only the input channels selected as
active by the configuration register, saving 2mA per
channel (typ). The wake-up time for any channel turned
on with the configuration register is 2s (typ) when
ALLON is low. The wake-up time with ALLON high is
only 0.01s. New configuration-register information
does not become active until the next CONVST falling
edge. Therefore, when using software to control power
states (ALLON = 0), pulse CONVST low once before
applying the actual CONVST signal (Figure 3). With an
external clock, apply at least 15 clock cycles before
the second CONVST. If using internal-clock mode, wait
at least 1.5s or until the first EOC before generating
the second CONVST.
Figure 2. Typical Input Circuit
CH_
R1
R2
VBIAS
CPAR
1pF
5pF
MAX1316–MAX1318
MAX1320–MAX1322
MAX1324–MAX1326
INPUT RANGE (V)
0 TO +5
±5
±10
R1 (k)
3.33
6.67
13.33
R2 (k)
5.00
2.86
2.35
VBIAS (V)
0.90
2.50
2.06
Table 1. Conversion Times Using the
Internal Clock
NUMBER OF CHANNELS
INTERNAL-CLOCK
CONVERSION TIME
1
1.6
2
1.9
3
2.2
4
2.5
5
2.8
6
3.1
7
3.4
8
3.7
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