參數(shù)資料
型號: MAX13043EETD+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/14頁
文件大小: 0K
描述: IC LEVEL TRANSLATOR 14-TDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
邏輯功能: 變換器,雙向
位數(shù): 4
輸入類型: CMOS
輸出類型: CMOS
數(shù)據(jù)速率: 100Mbps
通道數(shù): 4
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 6.5ns
電源電壓: 2.2 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 14-TDFN-EP(3x3)
包裝: 帶卷 (TR)
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
______________________________________________________________________________________
11
TDFN
(3mm x 3mm)
I/O VL1
4
3
2
1
11
12
13
14
N.C.
I/O VL2
EN
7
6
5
I/O VL4
VL
I/O VL3
N.C.
I/O VCC2
GND
I/O VCC1
8
9
10
I/O VCC4
VCC
I/O VCC3
MAX13042E–MAX13045E
*EP
+
*CONNECT EXPOSED PAD TO GROUND
UCSP
(1.54mm x 2.12mm)
A
B
C
12
3
4
I/O VCC3
I/O VCC1
I/O VCC4
I/O VCC2
VL
GND
VCC
EN
MAX13042E–MAX13045E
I/O VL3
I/O VL1
I/O VL4
I/O VL2
TOP VIEW
(BUMPS ON BOTTOM)
TOP VIEW
+
Pin Configurations
Ordering Information/Selector Guide (continued)
PART
PIN-
PACKAGE
I/O VL_ STATE DURING
SHUTDOWN
I/O VCC_ STATE DURING
SHUTDOWN
TOP
MARK
PKG CODE
MAX13043EEBC+T
12 UCSP-12
High Impedance
16.5k
Ω to GND
ADR
B12-3
MAX13043EETD+T
14 TDFN-EP**
High Impedance
16.5k
Ω to GND
ADF
T1433-2
MAX13044EEBC+T*
12 UCSP-12
16.5k
Ω to GND
High Impedance
ADS
B12-3
MAX13044EETD+T*
14 TDFN-EP**
16.5k
Ωto GND
High Impedance
ADG
T1433-2
MAX13045EEBC+T*
12 UCSP-12
16.5k
Ω to GND
16.5k
Ω to GND
ADT
B12-3
MAX13045EETD+T*
14 TDFN-EP**
16.5k
Ω to GND
16.5k
Ω to GND
ADH
T1433-2
Note: All devices operate over the -40°C to +85°C temperature
range.
+Denotes a lead-free package.
*Future product—contact factory for availability.
**EP = Exposed paddle.
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