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參數(shù)資料
| 型號(hào)： | MAX13043EETD+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LEVEL TRANSLATOR 14-TDFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 邏輯功能： | 變換器，雙向 |
| 位數(shù)： | 4 |
| 輸入類型： | CMOS |
| 輸出類型： | CMOS |
| 數(shù)據(jù)速率： | 100Mbps |
| 通道數(shù)： | 4 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 6.5ns |
| 電源電壓： | 2.2 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-TDFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
10
______________________________________________________________________________________
Shutdown Mode
The MAX13042E–MAX13045E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13042E–MAX13045E
feature an automatic shutdown mode that disables the
part when VCC is unconnected or less than VL.
Applications Information
Layout Recommendations
Use standard high-speed layout practices when
laying out a board with the MAX13042E–MAX13045E.
For example, to minimize line coupling, place all other
signal lines not connected to the MAX13042E–
MAX13045E at least 1x the substrate height of the
PCB away from the input and output lines of the
MAX13042E–MAX13045E.
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
errors, bypass VL and VCC to ground with 0.1F ceram-
ic capacitors. Place all capacitors as close to the
power-supply inputs as possible. For full ESD protec-
tion, bypass VCC with a 1F ceramic capacitor located
as close to the VCC input as possible.
Unidirectional vs. Bidirectional
Level Translator
The MAX13042E–MAX13045E bidirectional level trans-
lators can operate as a unidirectional device to trans-
late signals without inversion. These devices provide
the smallest solution (UCSP package) for unidirectional
level translation without inversion.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Use with External Pullup/
Pulldown Resistors
Due to the architecture of the MAX13042E–MAX13045E,
it is not recommended to use external pullup or pull-
down resistors on the bus. In certain applications, the
use of external pullup or pulldown resistors is desired to
have a known bus state when there is no active driver
on the bus. The MAX13042E–MAX13045E include inter-
nal pullup current sources that set the bus state when
the device is enabled. In shutdown mode, the state of
I/O VCC_ and I/O VL_ is dependent on the selected part
version (see the Ordering Information/Selector Guide).
Open-Drain Signaling
The MAX13042E–MAX13045E are designed to pass open-
drain as well as CMOS push-pull signals. When used with
open-drain signaling, the rise time will be dominated by the
interaction of the internal pullup current source and the par-
asitic load capacitance. The MAX13042E–MAX13045E
include internal rise-time accelerators to speed up transi-
tions, eliminating any need for external pullup resistors. For
applications such as I2C or 1-wire that require an external
pullup resistor, please consult the MAX3378E and
MAX3396E data sheets.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profiles, as well as the latest information on reliability testing
results, go to Maxim’s website at www.maxim-ic.com/ucsp
to find the Application Note: UCSP – A Wafer-Level Chip-
Scale Package.
Chip Information
PROCESS: BiCMOS
30
μA
VL
ENABLE
VCC
30
μA
BOOST
CIRCUIT
I/O VL_
VL
VCC
BOOST
CIRCUIT
VCC
VL
I/O VCC_
NOTE: THE MAX13042E–MAX13045E ARE ENABLED WHEN
VL < VCC AND EN = VL.
Figure 4. Simplified Functional Diagram for One I/O Line
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