參數(shù)資料
型號: MAX1301BEUP+T
廠商: Maxim Integrated Products
文件頁數(shù): 22/31頁
文件大小: 0K
描述: IC ADC 16BIT SER 4CH LP 20TSSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 16
采樣率(每秒): 115k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 879mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極;2 個差分,雙極
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. With an
input range equal to the ADC’s full-scale range, calcu-
late the ENOB as follows:
Total Harmonic Distortion (THD)
For the MAX1300/MAX1301, THD is the ratio of the
RMS sum of the input signal’s first four harmonic com-
ponents to the fundamental itself. This is expressed as:
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonic components.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next-largest spectral component.
THD
VVV
V
log
++
+
20
2
3
2
4
2
5
2
1
ENOB
SINAD
.
=
176
602
MAX1300/MAX1301
8- and 4-Channel, ±3 x VREF Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________
29
tAD
tAJ
INTCLK
(MODE 2)
ANALOG INPUT
TRACK AND HOLD
TRACK
HOLD
SAMPLE INSTANT
SCLK
(MODE 0)
13
14
15
SCLK
(MODE 1)
15
16
10
11
12
Figure 21. Aperture Diagram
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