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參數(shù)資料
| 型號： | MAX1301BEUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/31頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SER 4CH LP 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，雙極 |
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Digital Interface
The MAX1300/MAX1301 feature a serial interface that is
compatible with SPI/QSPI and MICROWIRE devices.
DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirec-
tional communication between the MAX1300/MAX1301
and the master at SCLK rates up to 10MHz (internal
clock mode, mode 2), 3.67MHz (external clock mode,
mode 0), or 4.39MHz (external acquisition mode, mode
1). The master, typically a microcontroller, should use
the CPOL = 0, CPHA = 0, SPI transfer format, as shown
in the timing diagrams of Figures 2, 3, and 4.
The digital interface is used to:
Select single-ended or true-differential input channel
configurations
Select the unipolar or bipolar input range
Select the mode of operation:
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
Initiate conversions and read results
Chip Select
(CS)
CS enables communication with the MAX1300/MAX1301.
When CS is low, data is clocked into the device from DIN
on the rising edge of SCLK and data is clocked out of
DOUT on the falling edge of SCLK. When CS is high,
activity on SCLK and DIN is ignored and DOUT is high
impedance allowing DOUT to be shared with other
peripherals. SSTRB is never high impedance and there-
fore cannot be shared with other peripherals.
Serial Strobe Output (SSTRB)
As shown in Figures 3 and 4, the SSTRB transitions high
to indicate that the ADC has completed a conversion
and results are ready to be read by the master. SSTRB
remains low in the external clock mode (Figure 2) and
consequently may be left unconnected. SSTRB is driven
high or low regardless of the state of CS, therefore
SSTRB cannot be shared with other peripherals.
MAX1300/MAX1301
8- and 4-Channel, ±3 x VREF Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________
19
001
010
011
100
101
110
111
0
(-3 x VREF)/2
-3 x VREF
+3 x VREF
(+3 x VREF)/2
EACH INPUT IS FAULT TOLERANT TO
±16.5V.
VREF = 4.096V.
(CH_)
-
AGND1
(V)
INPUT RANGE SELECTION BITS, R[2:0]
FSR
=
(3
x
V
REF
)/2
FSR
=
6V
FSR
=
(3
x
V
REF
)/2
FSR
=
3
x
V
REF
FSR
=
3
x
V
REF
FSR
=
3
x
V
REF
FSR
=
6
x
V
REF
Figure 7. Single-Ended Input Voltage Ranges
001
010
011
100
101
110
111
-3 x VREF
-6 x VREF
+6 x VREF
+3 x VREF
EACH INPUT IS FAULT TOLERANT TO
±16.5V.
VREF = 4.096V.
(CH_+)
-
(CH_-)
(V)
INPUT RANGE SELECTION BITS, R[2:0]
0
FSR
=
3
x
V
REF
FSR
=
6
x
V
REF
FSR
=
12
x
V
REF
Figure 8. Differential Input Voltage Ranges
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