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參數(shù)資料
| 型號： | MAX1301BEUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 14/31頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT SER 4CH LP 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，雙極 |
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Start Bit
Communication with the MAX1300/MAX1301 is accom-
plished using the three input data word formats shown
in Table 3. Each input data word begins with a start bit.
The start bit is defined as the first high bit clocked into
DIN with CS low when any of the following are true:
Data conversion is not in process and all data from
the previous conversion has clocked out of DOUT.
The device is configured for operation in external
clock mode (mode 0) and previous conversion-result
bits B15–B3 have clocked out of DOUT.
The device is configured for operation in external
acquisition mode (mode 1) and previous conversion-
result bits B15–B7 have clocked out of DOUT.
The device is configured for operation in internal
clock mode, (mode 2) and previous conversion-
result bits B15–B4 have clocked out of DOUT.
Output Data Format
Output data is clocked out of DOUT in offset binary for-
mat on the falling edge of SCLK, MSB first (B15). For
output binary codes, see the
Transfer Function section
and Figures 12, 13, and 14.
Configuring Analog Inputs
Each analog input has two configurable parameters:
Single-ended or true-differential input
Input voltage range
These parameters are configured using the analog input
configuration byte as shown in Table 2. Each analog
input has a dedicated register to store its input configura-
tion information. The timing diagram of Figure 15 shows
how to write to the analog input configuration registers.
Figure 16 shows DOUT and SSTRB timing.
Transfer Function
An ADC’s transfer function defines the relationship
between the analog input voltage and the digital output
code. Figures 12, 13, and 14 show the MAX1300/
MAX1301 transfer functions. The transfer function is
determined by the following characteristics:
Analog input voltage range
Single-ended or differential configuration
Reference voltage
The axes of an ADC transfer function are typically in least
significant bits (LSBs). For the MAX1300/MAX1301, an
LSB is calculated using the following equation:
where N is the number of bits (N = 16) and FSR is the
full-scale range (see Figures 7 and 8).
1
2
4 096
.
LSB
FSR
V
REF
N
=
×
MAX1300/MAX1301
8- and 4-Channel, ±3 x VREF Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________
21
INPUT VOLTAGE (V)
COMMON-MODE
VOLTAGE
(V)
12
6
0
-6
-12
-8
-4
0
4
8
12
-16
-18
18
Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = 3 x VREF)
INPUT VOLTAGE (V)
COMMON-MODE
VOLTAGE
(V)
12
6
0
-6
-12
-8
-4
0
4
8
12
-16
-18
18
Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 6 x VREF)
INPUT VOLTAGE (V)
COMMON-MODE
VOLTAGE
(V)
12
6
0
-6
-12
-8
-4
0
4
8
12
-16
-18
18
Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 12 x VREF)
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