參數(shù)資料
型號(hào)： MAX1198ECM+TD
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 2/22頁(yè)
文件大小： 0K
描述： IC ADC 8BIT 100MSPS DL 48-TQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 8
采樣率（每秒）： 100M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 314mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFP 裸露焊盤（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，雙極；2 個(gè)差分，雙極
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
10
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
COM
Common-Mode Voltage I/O. Bypass to GND with a
≥0.1F capacitor.
2, 6, 11, 14, 15
VDD
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2F in parallel with
0.1F.
3, 7, 10, 13, 16
GND
Analog Ground
4
INA+
Channel A Positive Analog Input. For single-ended operation connect signal source to INA+.
5
INA-
Channel A Negative Analog Input. For single-ended operation connect INA- to COM.
8
INB-
Channel B Negative Analog Input. For single-ended operation connect INB- to COM.
9
INB+
Channel B Positive Analog Input. For single-ended operation connect signal source to INB+.
12
CLK
Converter Clock Input
17
T/B
T/B Selects the ADC Digital Output Format
High: Two’s complement
Low: Straight offset binary
18
SLEEP
Sleep Mode Input
High: Disables both quantizers, but leaves the reference bias circuit active
Low: Normal operation
19
PD
Active-High Power-Down Input
High: Power-down mode
Low: Normal operation
20
OE
Active-Low Output Enable Input
High: Digital outputs disabled
Low: Digital outputs enabled
21
D7B
Three-State Digital Output, Bit 7 (MSB), Channel B
22
D6B
Three-State Digital Output, Bit 6, Channel B
23
D5B
Three-State Digital Output, Bit 5, Channel B
24
D4B
Three-State Digital Output, Bit 4, Channel B
25
D3B
Three-State Digital Output, Bit 3, Channel B
26
D2B
Three-State Digital Output, Bit 2, Channel B
27
D1B
Three-State Digital Output, Bit 1, Channel B
28
D0B
Three-State Digital Output, Bit 0, Channel B
29, 30, 35, 36
N.C.
No Connection
31, 34
OGND
Output Driver Ground
32, 33
OVDD
Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2F in parallel
with 0.1F.
37
D0A
Three-State Digital Output, Bit 0, Channel A
38
D1A
Three-State Digital Output, Bit 1, Channel A
39
D2A
Three-State Digital Output, Bit 2, Channel A
40
D3A
Three-State Digital Output, Bit 3, Channel A
41
D4A
Three-State Digital Output, Bit 4, Channel A
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