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參數(shù)資料
| 型號： | MAX1185ECM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 20MSPS DUAL 48-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 20M |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 2.43W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極；2 個(gè)差分，單極；2 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 1396 (CN2011-ZH PDF) |
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
12
______________________________________________________________________________________
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1185 is determined by the
internally generated voltage difference between REFP
(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The
full-scale range for both on-chip ADCs is adjustable
through the REFIN pin, which is provided for this purpose.
REFOUT, REFP, COM (VDD/2), and REFN are internally
buffered low-impedance outputs.
The MAX1185 provides three modes of reference operation:
Internal reference mode
Buffered external reference mode
Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor-divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a > 10nF capacitor to
GND. In internal reference mode, REFOUT, COM, REFP,
and REFN become low-impedance outputs.
In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu-
rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or con-
nected to REFIN through a > 10kΩ resistor.
In unbuffered external reference mode, connect REFIN to
GND. This deactivates the on-chip reference buffers for
REFP, COM, and REFN. With their buffers shut down,
these nodes become high impedance and may be driven
through separate, external reference sources.
Clock Input (CLK)
The MAX1185’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low jit-
ter and fast rise and fall times (< 2ns). In particular, sam-
pling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR performance
of the on-chip ADCs as follows:
SNRdB = 20 x log10 (1/[2π x fIN x tAJ])
where fIN represents the analog input frequency and tAJ
is the time of the aperture jitter.
Clock jitter is especially critical for undersampling appli-
cations. The clock input should always be considered as
an analog input and routed away from any analog input
or other digital signal lines.
The MAX1185 clock input operates with a voltage thresh-
old set to VDD/2. Clock inputs with a duty cycle other
than 50%, must meet the specifications for high and low
periods as stated in the
Electrical Characteristics.
System Timing Requirements
Figure 3 shows the relationship between clock and
analog input, A/B indicator, and the resulting CHA/CHB
data output. CHA and CHB data are sampled on the
rising edge of the clock signal. Following the rising
edge of the 5th clock cycles, the digitized value of the
original CHA sample is presented at the output, fol-
lowed one half-clock cycle later by the digitized value
of the original CHB sample.
A channel selection signal (A/B indicator) allows the user
to determine which output data represents which input
channel. With A/B = 1, digitized data from CHA is present
at the output and with A/B = 0 digitized data from CHB is
present.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (
OE), Channel
Selection (A/B)
All digital outputs, D0A/B–D9A/B (CHA or CHB data) and
A/B are TTL/CMOS logic-compatible. The output coding
can be chosen to be either offset binary or two’s comple-
ment (Table 1) controlled by a single pin (T/B). Pull T/B
low to select offset binary and high to activate two’s com-
plement output coding. The capacitive load on the digital
outputs D0A/B–D9A/B should be kept as low as possible
(< 15pF), to avoid large digital currents that could feed
back into the analog portion of the MAX1185, thereby
degrading its dynamic performance. Using buffers on
the digital outputs of the ADCs can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1185,
small-series resistors (e.g., 100Ω) may be added to the
digital output paths close to the MAX1185.
Figure 4 displays the timing relationship between output
enable and data output valid as well as power-
down/wake-up and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1185 offers two power-save modes—sleep
and full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to
2.8mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling OE high forces
the digital outputs into a high-impedance state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1185ECM-T | 制造商:Maxim Integrated Products 功能描述:DUAL, 10-BIT, 20MSPS, +3V, LOW-POWER ADC W/ I - Tape and Reel |
| MAX1185ECM-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1186ECM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX1186ECM+D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 2Ch 40Msps High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1186ECM+TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 2Ch 40Msps High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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