參數(shù)資料
型號: MAX1185ECM+D
廠商: Maxim Integrated Products
文件頁數(shù): 21/21頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 20MSPS DUAL 48-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 250
位數(shù): 10
采樣率(每秒): 20M
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 2.43W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 托盤
輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極;2 個差分,單極;2 個差分,雙極
產(chǎn)品目錄頁面: 1396 (CN2011-ZH PDF)
MAX1185
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
_______________________________________________________________________________________
9
Pin Description
PIN
NAME
FUNCTION
1
COM
Common-Mode Voltage Input/Output. Bypass to GND with a
≥ 0.1F capacitor.
2, 6, 11, 14, 15
VDD
Analog Supply Voltage. Bypass each supply pin to GND with a 0.1F capacitor. Analog
supply accepts a 2.7V to 3.6V input range.
3, 7, 10, 13, 16
GND
Analog Ground
4
INA+
Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
5
INA-
Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
8
INB-
Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
9
INB+
Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
12
CLK
Converter Clock Input
17
T/B
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.
18
SLEEP
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.
19
PD
Power-Down Input.
High: Power-down mode.
Low: Normal operation.
20
OE
Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.
21–29
N.C.
Do not connect.
30
A/B
A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0)
to be present on the output. A/B follows the external clock signal with typically 6ns delay.
31, 34
OGND
Output Driver Ground
32, 33
OVDD
Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1F capacitor. Output
driver supply accepts a 1.7V to 3.6V input range.
35
D0A/B
Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects
channel A or channel B data.
36
D1A/B
Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A
or channel B data.
37
D2A/B
Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A
or channel B data.
38
D3A/B
Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A
or channel B data.
39
D4A/B
Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A
or channel B data.
40
D5A/B
Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A
or channel B data.
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