參數(shù)資料
型號(hào)： MAX11665AUT+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 0K
描述： ADC 12BIT 500KSPS 1CH SOT23-6
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 696mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
20 _____________________________________________________________________________________
MAX11661–MAX11666
500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Detailed Description
The MAX11661–MAX11666 are fast, 12-/10-/8-bit, low-
power, single-supply ADCs. The devices operate from
a 2.2V to 3.6V supply and consume only 2.98mW
(VDD = 2.2V) or 4.37mW (VDD = 3V). These devices
are capable of sampling at full rate when driven by
an 8MHz clock. The dual-channel devices provide a
separate digital supply input (OVDD) to power the digi-
tal interface enabling communication with 1.5V, 1.8V,
2.5V, or 3V digital systems.
The conversion result appears at DOUT, MSB first, with a
leading zero followed by the 12-bit, 10-bit, or 8-bit result.
A 12-bit result is followed by two trailing zeros, a 10-bit
result is followed by four trailing zeros, and an 8-bit result
is followed by six trailing zeros. See Figures 1 and 5.
The dual-channel devices feature a dedicated refer-
ence input (REF). The input signal range for AIN1/AIN2
is defined as 0V to VREF with respect to AGND. The
single-channel devices use VDD as the reference. The
input signal range of AIN is defined as 0V to VDD with
respect to GND.
These ADCs include a power-down feature allowing
minimized power consumption at 2.5FA/ksps for lower
throughput rates. The wake-up and power-down feature
is controlled by using the SPI interface as described in
the Operating Modes section.
Serial Interface
The devices feature a 3-wire serial interface that directly
connects to SPI, QSPI, and MICROWIRE devices without
external logic. Figures 1 and 5 show the interface sig-
nals for a single conversion frame to achieve maximum
throughput.
The falling edge of CS defines the sampling instant.
Once CS transitions low, the external clock signal
(SCLK) controls the conversion.
The SAR core successively extracts binary-weighted bits
in every clock cycle. The MSB appears on the data bus
during the 2nd clock cycle with a delay outlined in the
timing specifications. All extracted data bits appear suc-
cessively on the data bus with the LSB appearing during
the 13th/11th/9th clock cycle for 12-/10-/8-bit operation.
The serial data stream of conversion bits is preceded by
a leading “zero” and succeeded by trailing “zeros.” The
data output (DOUT) goes into a high-impedance state
during the 16th clock cycle.
Figure 5. 10-/8-Bit Timing Diagrams
SCLK
12
3
45
67
89
10
11
12
13
14
15
16
1
SAMPLE
CS
DOUT
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
0
00
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00
SAMPLE
SCLK
CS
12
3
45
67
89
10
11
12
13
14
15
16
1
DOUT
0
00
D7
D6
D5
D4
D3
D2
D1
D0
00
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX11665EVKIT# 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 MAX11665 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
MAX11666 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:500ksps, Low-Power,Serial 12-/10-/8-Bit ADCs
MAX11666AUB 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:500ksps, Low-Power,Serial 12-/10-/8-Bit ADCs
MAX11666AUB/V 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:500ksps, Low-Power,Serial 12-/10-/8-Bit ADCs
MAX11666AUB/V+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 1-2Ch 12-Bit 500ksps ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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