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參數(shù)資料
| 型號： | MAX11609EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SERIAL 10BIT 8CH 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 94.4k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 666.7mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
16
Maxim Integrated
The device memory contains all of the conversion results
when the MAX11606–MAX11611 release SCL. The con-
verted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from a
multichannel scan. This does not apply to the
MAX11608/MAX11609 as each provides separate pins
for AIN7 and REF. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and point to the
first result. Note that only the current conversion results
are read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
A
71 1
R
CLOCK STRETCH
NUMBER OF BITS
P or Sr
1
8
RESULT 8 LSBs
8
RESULT 2 MSBs
A
1
A. SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
71 1
R
CLOCK STRETCH
A
NUMBER OF BITS
P or Sr
1
8
RESULT 1 ( 2MSBs)
A
1
A
8
RESULT 1 (8 LSBs) A
8
RESULT N (8LSBs)
A
1
8
RESULT N (8MSBs)
SLAVE TO MASTER
MASTER TO SLAVE
CLOCK STRETCH
tACQ1
tCONV2
tACQ2
tCONVN
tACQN
tCONV
tACQ
1
tCONV1
Figure 10. Internal Clock Mode Read Cycles
SLAVE ADDRESS
tCONV1
tACQ1
tACQ2
tCONVN
tACQN
tCONV
tACQ
NUMBER OF BITS
1
8
A
1
S
1
A
71 1
R
S
1
71 1
R
P OR Sr
1
8
A
1
A
8
A
8
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
SLAVE ADDRESS
P OR Sr
RESULT (8 LSBs)
8
A
1
RESULT (2 MSBs)
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
RESULT 1 (2 MSBs)
RESULT 2 (8 LSBs)
RESULT N (8 LSBs)
A
1
8
RESULT N (2 MSBs)
A
Figure 11. External Clock Mode Read Cycle
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