Low-Power, 4-/8-/12-Channel, I2C, 10-Bit ADCs in Ultra-Small P" />
參數(shù)資料
型號(hào)： MAX11609EEE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 4/22頁(yè)
文件大?。?/td> 0K
描述： IC ADC SERIAL 10BIT 8CH 16-QSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
采樣率（每秒）： 94.4k
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 666.7mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
12
Maxim Integrated
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition followed by a slave
address. When idle, the MAX11606–MAX11611 continu-
ously wait for a START condition followed by their slave
address. When the MAX11606–MAX11611 recognize
their slave address, they are ready to accept or send
data. The slave address has been factory programmed
and is always 0110100 for the MAX11606/MAX11607,
0110011 for the MAX11608/MAX11609, and 0110101 for
MAX11610/MAX11611 (Figure 7). The least significant bit
(LSB) of the address byte (R/W) determines whether the
master is writing to or reading from the MAX11606–
MAX11611 (R/W = 0 selects a write condition, R/W = 1
selects a read condition). After receiving the address, the
MAX11606–MAX11611 (slave) issues an acknowledge by
pulling SDA low for one clock cycle.
Bus Timing
At power-up, the MAX11606–MAX11611 bus timing is
set for fast mode (F/S mode), allowing conversion rates
up to 22.2ksps. The MAX11606–MAX11611 must oper-
ate in high-speed mode (HS mode) to achieve conver-
sion rates up to 94.4ksps. Figure 1 shows the bus timing
for the MAX11606–MAX11611’s 2-wire interface.
HS Mode
At power-up, the MAX11606–MAX11611 bus timing is
set for F/S mode. The bus master selects HS mode by
addressing all devices on the bus with the HS-mode
master code 0000 1XXX (X = don’t care). After success-
fully receiving the HS-mode master code, the
MAX11606–MAX11611 issue a not-acknowledge, allow-
ing SDA to be pulled high for one clock cycle (Figure 8).
After the not-acknowledge, the MAX11606–MAX11611
are in HS mode. The bus master must then send a
repeated START followed by a slave address to initiate
HS-mode communication. If the master generates a
STOP condition the MAX11606–MAX11611 returns to
F/S mode.
01
1
00
0
R/W
A
SLAVE ADDRESS
MAX11606/MAX11607
S
SCL
SDA
1
234
567
89
DEVICE
SLAVE ADDRESS
0110100
0110011
MAX11606/MAX11607
MAX11608/MAX11609
0110101
MAX11610/MAX11611
Figure 7. MAX11606/MAX11607 Slave Address Byte
000
1
0X
X
A
HS-MODE MASTER CODE
SCL
SDA
S
Sr
F/S MODE
HS MODE
Figure 8. F/S-Mode to HS-Mode Transfer
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