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參數(shù)資料
| 型號： | MAX11609EEE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 22/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SERIAL 10BIT 8CH 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 94.4k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 666.7mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極 |
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
9
Maxim Integrated
Detailed Description
The MAX11606–MAX11611 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX11606/MAX11607
are 4-channel ADCs, the MAX11608/MAX11609 are
8-channel ADCs, and the MAX11610/MAX11611 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 2 shows the simplified internal structure
for the MAX11610/MAX11611.
Power Supply
The MAX11606–MAX11611 operates from a single sup-
ply and consumes 670A (typ) at sampling rates up to
94.4ksps. The MAX11607/MAX11609/MAX11611 feature
a 2.048V internal reference and the MAX11606/
MAX11608/MAX11610 feature a 4.096V internal refer-
ence. All devices can be configured for use with an
external reference from 1V to VDD.
Analog Input and Track/Hold
The MAX11606–MAX11611 analog-input architecture
contains an analog-input multiplexer (mux), a fully dif-
ferential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog-input multiplexer con-
nects CT/H between the analog input selected by
CS[3:0] (see the
Configuration/Setup Bytes (Write
Cycle) section) and GND (Table 3). In differential mode,
the analog- input multiplexer connects CT/H to the + and
- analog inputs selected by CS[3:0] (Table 4).
During the acquisition interval, the T/H switches are in
the track position and CT/H charges to the analog input
ANALOG
INPUT
MUX
AIN1
AIN11/REF
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX11610)
2.048V (MAX11611)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
AND RAM
REF
T/H
10-BIT
ADC
VDD
GND
MAX11610
MAX11611
Figure 2. MAX11610/MAX11611 Functional Diagram
VDD
IOL
IOH
VOUT
400pF
SDA
Figure 3. Load Circuit
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