- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1935 > MAX11359AETL+T (Maxim Integrated Products)IC DAS SYSTEM 16BIT 40-TQFN PDF資料下載
參數(shù)資料
| 型號： | MAX11359AETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 51/67頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS SYSTEM 16BIT 40-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 512 |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當(dāng)前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
MAX11359A
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
55
Maxim Integrated
The STATUS register contains the status bits of events in
various system blocks. Any status bits not masked in the
IMSK register cause an interrupt on INT. Some of the
status bit setting events (GPI, WAKEUP, ALARM, DRDY)
can be directed to UPIO_ to provide multiple C inter-
rupt inputs. There are no specific mask bits for the UPIO
interrupt signals since the bits are effectively masked by
selecting a different function for UPIO. The STATUS bits
always record the triggering event(s), even for masked
bits, which do not generate an interrupt on INT. It is pos-
sible to set multiple STATUS bits during a single INT
interrupt event. Clear all STATUS bits except for ADD
and ADOU by reading the STATUS register. During a
STATUS register read, INT deasserts when the first
STATUS data bit (LDVD) reads out (9th rising SCLK) and
remains deasserted until shortly after the last STATUS
data bit (~15ns). At this point, INT reasserts if any
STATUS bit is set during the STATUS register read. If the
STATUS register is partially read (i.e., the read is aborted
midway), none of the STATUS bits are cleared. New
events occurring during a STATUS register read, or
events that persist after reading the STATUS bits result in
another interrupt immediately after the STATUS register
read finishes. This is a read-only register.
LDVD: Low DVDD voltage-detector status bit. LDVD =
1 indicates DVDD is below the +1.8V threshold; other-
wise LDVD = 0. LDVD clears during the STATUS register
read as long as the condition does not persist.
Otherwise, the LDVD bit reasserts immediately. If the
DVDD low voltage detector is disabled, LDVD = 0. The
power-on default is 0.
LCPD: Low CPOUT voltage-detector status bit. LCPD =
1 indicates CPOUT is below the +2.7V threshold; other-
wise LCPD = 0. LCPD clears during the STATUS regis-
ter read as long as the condition does not persist.
Otherwise the LCPD bit reasserts immediately. LCPD =
0 when the CPOUT low voltage detector is disabled.
The power-on default is 0.
ADOU: ADC overflow/underflow status bit. ADOU = 1
indicates an ADC underflow or overflow condition in the
current ADC result. New conversions that are valid
clear the ADOU bit. ADOU = 0 when the ADC data is
valid or the ADC is disabled (ADCE = 0). An underflow
condition occurs when the ADC data is theoretically
less than 0000 hex in unipolar mode and less than
8000 hex in bipolar mode. An overflow condition occurs
when the ADC data is theoretically greater than FFFF
hex in unipolar mode and greater than 7FFF hex in
bipolar mode. Use this bit to determine the validity of
an ADC result at the maximum or minimum code values
(i.e., 0000 hex or FFFF hex for unipolar mode and 8000
hex and 7FFF hex for bipolar mode). The power-on
default is 0. Reading the STATUS register does not
clear the ADOU bit.
SDC: Signal-detect comparator status bit. When SDC =
1, the positive input to the signal-detect comparator
exceeds the negative input plus the programmed thresh-
old voltage. The SDC bit clears during the STATUS regis-
ter read unless the condition remains true. The SDC bit
also deasserts when the signal-detect comparator pow-
ers down (SDCE = 0). The power-on default is 0.
CRDY: High-frequency-clock ready status bit. CRDY =
1 indicates a locked high-frequency clock to the 32kHz
reference frequency by the FLL. The CRDY bit clears
during the STATUS register read. This bit only asserts
after power-up or after enabling the FLL using the FLLE
bit. The power-on default is 0.
ADD: ADC-done status bit. ADD = 1 indicates a com-
pleted ADC conversion or calibration. Clear the ADD bit
by reading the appropriate ADC data, offset, or gain-cali-
bration registers. The ADC status bit also clears when a
new ADC result updates to the data or calibration regis-
ters (i.e., it follows the assertion level of the UPIO =
DRDY signal). Reading the STATUS register does not
clear this bit. This bit is equivalent to the DRDY signal
available through UPIO_. The power-on default is 0.
hysteresis helps eliminate chatter when running directly off
unregulated batteries. If DVDD falls below +1.3V (typ), the
power-on reset circuitry is enabled and the HYSE bit is
deasserted setting the hysteresis back to +20mV. The
power-on default is 0.
RSTE:
RESET output enable bit. Set RSTE = 1 to
enable
RESET to be controlled by the +1.8V DVDD low-
supply-voltage detector, and set RSTE = 0 to disable
this control. The power-on default is 1.
MSB
LDVD
LCPD
ADOU
SDC
CRDY
ADD
ALD
X
LSB
UPR4
UPR3
UPR2
UPR1
UPF4
UPF3
UPF2
UPF1
STATUS Register (Power-On State: 0000 000X 0000 0000)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX115CAX+ | IC DAS SYSTEM 12BIT 36-SSOP |
| MAX1221BETX+T | IC ADC/DAC 12BIT W/FIFO 36TQFNEP |
| MAX1257BETM+T | IC ADC/DAC 12BIT 48-TQFN |
| MAX125CCAX+D | IC DAS 14BIT 2X4CH 36-SSOP |
| MAX1271AENG+ | IC ADC 12BIT 8CH 24-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1135BCAP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1135BCAP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 150ksps 3.3V Single Supply RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1135BCAP+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 150ksps 3.3V Single Supply RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1135BCAP-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1135BEAP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。