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參數(shù)資料
| 型號： | MAX1134BEAP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 150KSPS 20-SSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 150k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 26.4mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
MAX1134/MAX1135
16-Bit ADCs, 150ksps, 3.3V Single Supply
______________________________________________________________________________________
11
SCLK
DOUT
DIN
SSTRB
CS
4
18
START
M1
M0
P2
P1
P0
UNI/
BIP
INT/
EXT
9
21
24
B4
B14
B15
MSB
B3
B1
B0
LSB
B2
FILLED WITH
ZEROS
tACQ
tCONV
10
B13
Figure 5. Internal Clock Mode Timing, Short Acquisition
In long acquisition mode, when using external clock,
SSTRB pulses high for one clock period after the 15th
falling edge of SCLK following the start bit. The MSB of
the conversion is available at DOUT on the 16th falling
edge of SCLK (Figure 3).
In external clock mode, SSTRB is high impedance when
CS is high (Figure 4). CS is normally held low during the
entire conversion. If CS goes high during the conver-
sion, SCLK is ignored until CS goes low. This allows
external clock mode to be used with 8-bit bytes.
Internal Clock
In internal clock mode, the MAX1134/MAX1135 gener-
ate their own conversion clock. This frees the micro-
processor from the burden of running the SAR
conversion clock, and allows the conversion results to
be read back at the processor’s convenience, at any
clock rate up to 4MHz.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB is low for
a maximum of 7s, during which time SCLK should
remain low for best noise performance. An internal reg-
ister stores data when the conversion is in progress.
SCLK clocks the data out of the internal storage regis-
ter at any time after the conversion is complete.
The MSB of the conversion is available at DOUT when
SSTRB goes high. The subsequent 15 falling edges on
SCLK shift the remaining bits out of the internal storage
register (Figure 5). CS does not need to be held low
once a conversion is started.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Figure 6 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted into
the MAX1134/MAX1135 at clock rates up to 4MHz, pro-
P0 CLOCKED IN
tSSTRB
tCONV
tSCK
tCSS
SSTRB
SCLK
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
tCSH
CS
Figure 6. Internal Clock Mode SSTRB Detailed Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1135 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit ADCs.150ksps.3.3V Single Supply |
| MAX11358B | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor |
| MAX11358BCTL+ | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor |
| MAX11358BETL+ | 功能描述:ADC / DAC多通道 Integrated Circuits (ICs) Analog to Digital Converters - Special Purpose - IC DAS SYSTEM 16BIT 40-TQFN RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX11358BETL+T | 功能描述:ADC / DAC多通道 Integrated Circuits (ICs) Analog to Digital Converters - Special Purpose - IC DAS SYSTEM 16BIT 40-TQFN RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
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