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參數(shù)資料
| 型號(hào)： | MAX1133BEAP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 15/19頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 200KSPS 20-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 55mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
_______________________________________________________________________________________
5
Note 1: Tested at AVDD = DVDD = +5V, bipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nulled.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period, clock has 50% duty cycle.
Includes the acquisition time.
Note 5: ADC performance is limited by the converter’s noise floor, typically 300Vp-p.
Note 6: When an external reference has a different voltage than the specified typical value, the full scale of the ADC will scale
proportionally.
Note 7: Electrical characteristics are guaranteed from AVDD(MIN) = DVDD(MIN) to AVDD(MAX) = DVDD(MAX). For operations beyond
this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 8: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
TIMING CHARACTERISTICS (Figures 5 and 6)
(AVDD = DVDD = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Acquisition Time
tACQ
1.14
s
DIN to SCLK Setup
tDS
50
ns
DIN to SCLK Hold
tDH
0ns
SCLK to DOUT Valid
tDO
70
ns
CS Fall to DOUT Enable
tDV
CLOAD = 50pF
80
ns
CS Rise to DOUT Disable
tTR
CLOAD = 50pF
80
ns
CS to SCLK Rise Setup
tCSS
100
ns
CS to SCLK Rise Hold
tCSH
0ns
SCLK High Pulse Width
tCH
80
ns
SCLK Low Pulse Width
tCL
80
ns
SCLK Fall to SSTRB
tSSTRB
CLOAD = 50pF
80
ns
CS Fall to SSTRB Enable
tSDV
CLOAD = 50pF, external clock mode
80
ns
CS Rise to SSTRB Disable
tSTR
CLOAD = 50pF, external clock mode
80
ns
SSTRB Rise to SCLK Rise
tSCK
Internal clock mode
0
ns
RST Pulse Width
tRS
208
ns
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