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參數(shù)資料
| 型號： | MAX1124EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/17頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT PAR 250MSPS 68QFN |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 250M |
| 數(shù)據(jù)接口： | LVDS，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 657mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設(shè)備封裝： | * |
| 包裝： | * |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個差分，單極 |
MAX1124
Detailed Description—Theory
of Operation
The MAX1124 uses a fully differential, pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy and linearity, while minimizing power
consumption and die size.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a common-
mode voltage of 1.4V, and accept a differential analog
input voltage swing of ±0.3125V each, resulting in a typi-
cal differential full-scale signal swing of 1.25VP-P.
INP and INN are buffered prior to entering each track-
and-hold (T/H) stage and are sampled when the differen-
tial sampling clock signal transitions high. A 2-bit ADC
following the first T/H stage then digitizes the signal, and
controls a 2-bit digital-to-analog converter (DAC).
Digitized and reference signals are then subtracted,
resulting in a fractional residue signal that is amplified
before it is passed on to the next stage through another
T/H amplifier. This process is repeated until the applied
input signal has successfully passed through all stages
of the 10-bit quantizer. Finally, the digital outputs of all
stages are combined and corrected for in the digital cor-
rection logic to generate the final output code. The result
is a 10-bit parallel digital output word in user-selectable
two’s complement or binary output formats with LVDS-
compatible output levels. See Figure 1 for a more
detailed view of the MAX1124 architecture.
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
10
______________________________________________________________________________________
CLOCK-
DIVIDER
CONTROL
CLOCK
MANAGEMENT
T/H
10-BIT PIPELINE
QUANTIZER CORE
REFERENCE
LVDS
DATA PORT
10
COMMON-MODE
BUFFER
INPUT
BUFFER
CLKDIV
CLKP
CLKN
INP
INN
REFIO REFADJ
2.2k
Ω
2.2k
Ω
DCLKP
DCLKN
D0P/N–D9P/N
ORP
ORN
MAX1124
Figure 1. MAX1124 Block Diagram
AVCC
AGND
INN
INP
TO COMMON-MODE INPUT
2.2k
Ω
TO COMMON-MODE INPUT
2.2k
Ω
Figure 2. Simplified Analog Input Architecture
REFERENCE
BUFFER
REFIO
REFADJ
AVCC
AVCC/2
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
ADC FULL-SCALE = REFT - REFB
G
1V
1k
Ω
0.1
μF
REFERENCE
SCALING
AMPLIFIER
REFT
REFB
Figure 3. Simplified Reference Architecture
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參數(shù)描述 |
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| MAX1124EVKIT | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Evaluation Kit for the MAX1121 MAX1122 MAX1123 MAX1124 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX1125 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125AIBH | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125AIDO | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125BIBH | 制造商:Maxim Integrated Products 功能描述:44 PIN COUNT UCSP PACKAGE TYPE - Bulk |
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