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參數(shù)資料
| 型號： | MAX1124EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/17頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT PAR 250MSPS 68QFN |
| 標準包裝： | 2,500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 250M |
| 數(shù)據(jù)接口： | LVDS，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 657mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應商設備封裝： | * |
| 包裝： | * |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個差分，單極 |
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
_______________________________________________________________________________________
9
Pin Description (continued)
PIN
NAME
FUNCTION
26, 45, 61
OGND
Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41, 44, 60
OVCC
Digital Supply Voltage. Bypass with a 0.1F capacitor for best decoupling results.
29–32
N.C.
No Connection. Do not connect to these pins.
33
D0N
Complementary Output Bit 0 (LSB)
34
D0P
True Output Bit 0 (LSB)
35
D1N
Complementary Output Bit 1
36
D1P
True Output Bit 1
37
D2N
Complementary Output Bit 2
38
D2P
True Output Bit 2
39
D3N
Complementary Output Bit 3
40
D3P
True Output Bit 3
42
DCLKN
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock. There is a 2.1ns delay
between CLKN and DCLKN.
43
DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock. There is a 2.1ns delay between CLKP
and DCLKP.
46
D4N
Complementary Output Bit 4
47
D4P
True Output Bit 4
48
D5N
Complementary Output Bit 5
49
D5P
True Output Bit 5
50
D6N
Complementary Output Bit 6
51
D6P
True Output Bit 6
52
D7N
Complementary Output Bit 7
53
D7P
True Output Bit 7
54
D8N
Complementary Output Bit 8
55
D8P
True Output Bit 8
56
D9N
Complementary Output Bit 9 (MSB)
57
D9P
True Output Bit 9 (MSB)
58
ORN
Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
59
ORP
True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP
flags this condition by transitioning high.
68
T/B
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input
controls the digital output format of the MAX1124.
T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format
T/B = 1: Binary output format
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相關代理商/技術參數(shù) |
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|---|---|
| MAX1124EVKIT | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 Evaluation Kit for the MAX1121 MAX1122 MAX1123 MAX1124 RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX1125 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125AIBH | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125AIDO | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125BIBH | 制造商:Maxim Integrated Products 功能描述:44 PIN COUNT UCSP PACKAGE TYPE - Bulk |
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