參數(shù)資料
型號(hào): MAX1111EPE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs
中文描述: 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 7/20頁
文件大?。?/td> 284K
代理商: MAX1111EPE
M
+2.7V, Low-Power, Multic hannel,
S erial 8-Bit ADCs
_______________________________________________________________________________________
7
______________________________________________________________Pin Desc ription
16
SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1110/
MAX1111 begin the A/D conversion and goes high when the conversion is done.
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when
CS
is high (external clock mode only).
20
V
DD
Positive Supply Voltage, +2.7V to +5.5V
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless
CS
is low. When
CS
is
high, DOUT is high impedance. The voltage at
CS
may exceed V
DD
(up to 5.5V).
19
SCLK
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
SCLK also sets the conversion speed (duty cycle must be 45% to 55%). The voltage at
SCLK may exceed V
DD
(up to 5.5V).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge. The voltage at DIN may
exceed V
DD
(up to 5.5V).
12
13
REFOUT
AGND
Internal Reference Generator Output. Bypass with a 1μF capacitor to AGND.
Analog Ground
14
DGND
Digital Ground
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS
is high.
15
DOUT
10
SHDN
Three-Level Shutdown Input. Normally floats. Pulling
SHDN
low shuts the MAX1110/
MAX1111 down to 10μA (max) supply current; otherwise, the devices are fully opera-
tional. Pulling
SHDN
high shuts down the internal reference.
11
REFIN
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
the internal reference.
5–8
CH4–CH7
Sampling Analog Inputs
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
Must be stable to ±0.5LSB.
1–4
CH0–CH3
Sampling Analog Inputs
+3V
3k
C
LOAD
DGND
DOUT
C
LOAD
DGND
3k
DOUT
a)
High-Z to V
OH
and V
OL
to V
OH
b)
High-Z to V
OL
and V
OH
to V
OL
Figure 1. Load Circuits for Enable Time
+3V
3k
C
LOAD
DGND
DOUT
C
LOAD
DGND
3k
DOUT
a)
V
OH
to High-Z
b)
V
OL
to High-Z
Figure 2. Load Circuits for Disable Time
12
16
14
15
13
8
9
10
11
6
7
1–4
5
9
COM
PIN
MAX1111
NAME
FUNCTION
MAX1110
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