參數(shù)資料
型號(hào): MAX1111EPE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: +2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs
中文描述: 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 14/20頁
文件大?。?/td> 284K
代理商: MAX1111EPE
M
+2.7V, Low-Power, Multic hannel,
S erial 8-Bit ADCs
14
______________________________________________________________________________________
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
15
17
START
SEL2 SEL1 SEL0
BIP
DIF
PD1
PD0
B7
B6
B1
B0
t
ACQ
4μs (f
SCLK
= 500kHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
25μs TYP
A/D STATE
2
3
5
6
7
9
10
11
16
18
t
CONV
Figure 10. Internal Clock Mode Timing
PD0 CLOCK IN
t
SSTRB
t
CSH
t
CONV
t
SCK
SSTRB
SCLK
t
CSS
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 11. Internal Clock Mode SSTRB Detailed Timing
Internal Clock
Internal clock mode frees the μP from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz. SSTRB goes
low at the start of the conversion and then goes high
when the conversion is complete. SSTRB is low for
25μs (typically), during which time SCLK should remain
low for best noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the second falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 10).
CS
does
not need to be held low once a conversion is started.
Pulling
CS
high prevents data from being clocked into
the MAX1110/MAX1111 and three-states DOUT, but it
does not adversely affect an internal clock-mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when
CS
goes high.
Figure 11 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1110/MAX1111 at clock rates up to 2MHz, pro-
vided that the minimum acquisition time, t
ACQ
, is kept
above 1μs.
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