參數(shù)資料
型號: MAX11043ATL+
廠商: Maxim Integrated Products
文件頁數(shù): 15/33頁
文件大小: 0K
描述: IC ADC 16BIT W/DAC 40-TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
類型: ADC,DAC
分辨率(位): 16 b
采樣率(每秒): 9.6M
數(shù)據(jù)接口: 串行
電壓電源: 模擬和數(shù)字
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(6x6)
包裝: 管件
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
22
Maxim Integrated
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
0
PURGE4
PURGE3
PURGE2
PURGE1
PURGE0
Reference Register (10h)
Reserved<15:13>: Reserved. Set to 0.
PURGE4:PURGE0<12:8>: Filter purge interval.
Straight binary.
00h = first available sample is presented (default).
1Fh = 31 results are discarded.
Digital filters retain a history of past input data. At
power-up and when changing the signal path, old data
requires purging before new output data is valid.
PURGE4(MSB):PURGE0 determine the number of sam-
ples to discard before a new result is valid. Each time
CONVRUN is taken high, N results are discarded
before EOC asserts low (where N is the decimal equiva-
lent of the binary representation of PURGE4:PURGE0).
Results prior to N+1 are overwritten. EOC asserts for
results N+1, N+2, N+3, etc., as long as CONVRUN
remains high. Taking CONVRUN low and then high
invokes another purge.
Purging of the sinc 5 filter requires five readings if
DECSEL (configuration register 08h, bit 0) = 1 and
three readings if DECSEL = 0. The minimum total purge
interval of the seven cascaded filters is one reading if
not used. If the filters are used, the total latency of the
programmable filters is the sum of the latency caused
by each stage. Set the appropriate delay for filter purg-
ing and settling time.
EXTREF<7>: Main reference selection.
1 = external reference applied to REFBP, internal refer-
ence buffer powered down.
0 = internal reference, bypass REFBP with 1F to
AGND (default).
EXBUF_<6:3>: ADC reference selection for each
channel.
1 = external reference applied to REF_ input, internal
switch open.
0 = using main internal reference, bypass REF_ with
1F to AGND (default).
EXBUFDAC<2>: Coarse DAC reference selection.
1 = external reference applied to REFDAC, internal ref-
erence buffer powered down.
0 = using main internal reference, bypass REFDAC
with 1F to AGND (default).
EXBUFDACH<1>: High reference for fine DAC.
1 = external reference applied to REFDACH, internal
reference buffer powered down.
0 = using high output from coarse DAC as reference,
bypass REFDACH with 1F to AGND (default).
EXBUFDACL<0>: Low reference for fine DAC.
1 = external reference applied to REFDACL, internal
reference buffer powered down.
0 = using low output from coarse DAC as reference,
bypass REFDACL with 1F to AGND (default).
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EXTREF
EXBUFA
EXBUFB
EXBUFC
EXBUFD
EXBUFDAC
EXBUFDACH
EXBUFDACL
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