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參數(shù)資料
| 型號(hào)： | MAX1003CAX+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 6BIT 90MSPS DL 36-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 6 |
| 采樣率（每秒）： | 90M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 941mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 4 個(gè)單端，單極；2 個(gè)差分，單極 |
_______________Detailed Description
Converter Operation
The MAX1003 contains two 6-bit analog-to-digital con-
verters (ADCs), a buffered voltage reference, and oscil-
lator circuitry. The ADCs use a flash conversion
technique to convert an analog input signal into a 6-bit
parallel digital output code. The MAX1003’s unique
design includes 63 fully differential comparators and a
proprietary encoding scheme that ensures no more
than 1LSB dynamic encoding error. The control logic
interfaces easily to most digital signal processors
(DSPs) and microprocessors (Ps) with +3.3V CMOS-
compatible logic interfaces. Figure 1 shows the
MAX1003 in a typical application.
Programmable Input Amplifiers
The MAX1003 has two (I and Q) programmable-gain
input amplifiers with a -0.5dB bandwidth of 55MHz and
true differential inputs. To maximize performance in
high-speed systems, each amplifier has less than 5pF
of input capacitance. The input amplifier gain is pro-
grammed, via the GAIN pin, to provide three possible
input full-scale ranges (FSRs) as shown in Table 1.
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________
5
______________________________________________________________Pin Description
PIN
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).
GAIN
1
FUNCTION
NAME
Positive I-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
IOCC+
2
I-Channel Noninverting Analog Input
IIN+
4
Negative I-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
IOCC-
3
+5V ±5% Supply. Bypass with a 0.01F capacitor to GND (pin 7).
VCC
6
+5V ±5% Supply. Bypass with a 0.01F capacitor to GND (pin 11).
VCC
8
Analog Ground
GND
7, 11, 12,
18, 19
I-Channel Inverting Analog Input
IIN-
5
Negative Oscillator/Clock Input
TNK-
10
Q-Channel Inverting Analog Input
QIN-
14
+5V ±5% Supply. Bypass with a 0.01F capacitor to GND (pin 12).
VCC
13
Negative Q-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
QOCC-
16
Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB).
DQ5–DQ0
20–25
Positive Q-Channel Offset-Correction Compensation. Connect a 0.22F capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
QOCC+
17
Q-Channel Noninverting Analog Input
QIN+
15
Positive Oscillator/Clock Input
TNK+
9
Digital Output Ground
OGND
27
I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB).
DI0–DI5
30–35
Digital Clock Output. Frames the output data.
DCLK
29
Digital Output Supply, +3.3V ±300mV. Bypass each with a 47pF capacitor to OGND (pin 27).
VCCO
26, 28
+5V ±5% Supply. Bypass with a 0.01F capacitor to GND (pin 19).
VCC
36
250
Open
125
VCC
GAIN
500
GND
INPUT FULL-SCALE RANGE
(mVp-p)
Table 1. Input Amplifier Programming
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