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參數(shù)資料
| 型號(hào)： | MAX1003CAX+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 6BIT 90MSPS DL 36-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 6 |
| 采樣率（每秒）： | 90M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 941mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；2 個(gè)差分，單極 |
MAX1003
Low-Power, 90Msps, Dual 6-Bit ADC
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(VCC = +5V ±5%, VCCO = 3.3V ±300mV, TA = +25°C, unless otherwise noted.)
Note 1: Best-fit straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3: PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in VCC supply voltage,
expressed in decibels.
Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22F at Q and I compensation inputs (Figures 2 and 3).
Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. tDCLK is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
GAIN = GND, open, VCC
GAIN = open (mid gain), fIN = 50MHz,
-1dB below full scale
GAIN = open (mid gain)
5.7
ENOBM
5.6
5.85
Effective Number of Bits
GAIN = open (mid gain)
GAIN = GND (low gain)
Q channel
I channel
dB
CONDITIONS
MHz
55
BW
Analog Input -0.5dB Bandwidth
Msps
90
fMAX
Maximum Sample Rate
-55
XTLK
GAIN = VCC (high gain)
Crosstalk Between ADCs
LSB
-0.5
0.5
OFF
Input Offset (Note 5)
-0.5
0.5
dB
35.5
37
SINAD
Signal-to-Noise plus Distortion
Ratio
Bits
5.85
ENOBL
5.8
ENOBH
(Note 5)
dB
-0.2
±0.1
0.2
AM
Amplitude Match Between
ADCs
LSB
-0.5
±0.25
0.5
OMM
Offset Mismatch Between ADCs
(Note 6)
ns
1.5
tSKEW
Data Valid Skew
ns
3.6
tPD
Clock to Data Propagation
Delay
degrees
-2
±0.5
2
PM
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Phase Match Between ADCs
TNK+ to DCLK (Note 6)
ns
5.3
tDCLK
Input to DCLK Delay
Figure 8
ns
7.5
tAD
Aperture Delay
Figure 8
clock
cycle
1
PD
Pipeline Delay
TIMING CHARACTERISTICS (Data outputs: RL = 1M, CL = 15pF)
DYNAMIC PERFORMANCE (Gain = open, external 90MHz clock (Figure 7), VINI = VINQ = 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
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