參數(shù)資料
型號： MA28140
廠商： Dynex Semiconductor Ltd.
英文描述： Packet Telecommand Decoder
中文描述： 包遙控解碼器
文件頁數(shù)： 36/72頁
文件大?。?/td> 857K
代理商： MA28140
MA28140
36/72
5.6 LOCAL BUS INTERFACE
This interface is used to access the external memory map.
It consists of the following signals:
LADR<10..0>: address bus (output),
LDAT<7..0>: data bus (input/output),
RWN: read write output,
LACK: memory acknowledge input,
RAMCSN: RAM chip select output,
ROMCSN: ROM chip select output,
LACCS: chip select output asserted for recovery LAC
counter access.
The Local bus cycle is started by asserting the RWN and
CSN signals and activating the LADR signal. It is ended by
asserting LACK signal. If extended access times are not
required, LACK can be permanently asserted. This interface
provides a bus fault timer which is enabled when CSN signals
are active and reset when LACK signal is active. If a reset
doesn’t occur within a minimum of 32 Tck (8 us for a 4 MHz
clock frequency) and a maximum of 64 Tck (16 us for a 4 MHz
clock frequency), the current Local bus cycle is aborted by
forcing CSN inactive. The functional timings corresponding to
the local bus interface are given in section 8.2.
Figure 19: CPDU Interface
CPDUSTN
CPDUEN
LDAT<7-0>
PTD
CPDU
External
Module
CPDUDIV
CPDU Interface
C
up to 256
CPDU outputs
5.7 MEMORIES
The PTD manages two types of memory:
RAM to temporarily store the received TC data and all
protocol variables (counter values, programmable key,
...). The RAM is organized in 2K words of 8 bits. In the
case when it is used to store the eight bits of the recovery
LAC counter, it should be non volatile.
ROM (1Kx8) to store the mission specific data and the
fixed Authentication key.
In order to allow the use of slow memories, an
acknowledge signal (LACK) is used to indicate when the
memory access is completed.
In order to save the 8 LSBs of recovery LAC counter in a
device different from the RAM, two different chip select signals
(RAMCSN and LACCS) are provided for the recovery LAC
counter access. Two different modes are provided to manage
the LAC counter select signals, these modes are selectable
with a configuration pin called AUTSL as follows:
AUTSL = 1: The recovery LAC counter is stored in RAM.
The PTD asserts the RAMCSN signal when it performs
the recovery LAC counter access.
AUTSL = 0: The recovery LAC counter is stored in a
device different from the RAM. The PTD asserts the
LACCS signal when it performs the recovery LAC counter
access. This non volatile memory could be for example
an EEPROM for low radiation requirements or relays for
radiation hardened recovery LACs.
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