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參數(shù)資料
| 型號： | MA28140 |
| 廠商： | Dynex Semiconductor Ltd. |
| 英文描述： | Packet Telecommand Decoder |
| 中文描述： | 包遙控解碼器 |
| 文件頁數(shù)： | 35/72頁 |
| 文件大?。?/td> | 857K |
| 代理商： | MA28140 |
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MA28140
35/72
Figure 17: Parallel MAP Interface
Figure 18: Parallel Telemetry Read Cycle
For a 4 MHz clock, the duration D is 10.24 ms if
CPDUDIV=0 and 2.048 ms if CPDUDIV=1. The maximum
duration (=128xD) is about 1.31 s if CPDUDIV=0, and 262 ms
if CPDUDIV=1. The delay between the time at which the
packet has been declared Legal and the execution of the
command instruction (rising edge of CPDUEN) can be any
value between 0.5 D and 1.5 D. The duration between two
instructions placed one after the other in the same CPDU
packet (from falling edge to rising edge of CPDUEN)
corresponds to about D.
5.5 CPDU INTERFACE
This interface consists of 3 signal lines:
CPDUSTN: CPDU address strobe output,
CPDUEN: CPDU enable output,
CPDUDIV: CPDU frequency divider input.
The CPDU interface provides the output signal CPDUSTN
in order to save the CPDU physical channel identifier present
on the local data bus LDAT<7..0> in an external latch (no
specific LADR address is associated with this data). This
CPDU identifier is used to demultiplex the command pulse
toward the selected CPDU output. The CPDUSTN signal can
be controlled by the LACK input. The CPDUEN signal is
representative of the command pulse as far as duration is
concerned. The pulse amplification should be made after
demultiplexing with external circuitry. The CPDUDIV signal
allows division of the pulse length specified in ref 2 by a factor
of 5, in order to get a better accuracy. Alternatively, this allows
the PTD to be used with a 1MHz clock frequency, instead of a
4 MHz clock.
Table 4: CPDU Pulse Lengths
COMMAND
PULSE LENGTH
(CLOCKS)
(CPUDIV=0)
40961
81921
163841
327681
655361
1310721
2621441
5242881
PULSE LENGTH
(CLOCKS)
(CPUDIV= 1)
8193
16385
32769
65537
131073
262145
524289
1048577
000
001
010
011
100
101
110
111
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