參數(shù)資料
型號(hào)： MA160014
廠商： Microchip Technology
文件頁數(shù)： 55/71頁
文件大?。?/td> 0K
描述： MOD PLUG-IN 44PIN PIC18LF45K22
標(biāo)準(zhǔn)包裝： 1
系列： PIC® XLP™ 18F
附件類型： 插拔式模塊（PIM）- PIC18LF45K22
適用于相關(guān)產(chǎn)品： PICDEM PIC18 Explorer，DM183032
2010-2012 Microchip Technology Inc.
DS41412F-page 59
PIC18(L)F2X/4XK22
4.0
RESET
The PIC18(L)F2X/4XK22 devices differentiate between
various kinds of Reset:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during power-managed modes
d)
Watchdog Timer (WDT) Reset (during
execution)
e)
Programmable Brown-out Reset (BOR)
f)
RESET
Instruction
g)
Stack Full Reset
h)
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
WDT Resets are covered in Section 24.3 “Watchdog
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred.
This
is
described
in
more
detail
in
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
BOR
is
covered
in
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD
Detect
OST/PWRT
LFINTOSC
POR
OST(2)
10-bit Ripple Counter
PWRT(2)
11-bit Ripple Counter
Enable OST(1)
Enable PWRT
Note 1:
See Table 4-2 for time-out situations.
2:
PWRT and OST counters are reset by POR and BOR. See Sections 4.4 and 4.5.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32
s
MCLRE
S
R
Q
Chip_Reset
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