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參數(shù)資料
| 型號： | M8813F3Y-90K1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 40/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F3Y-90K1T |
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M88 FAMILY
driven out to the pins if the Direction Register or
the output enable product term is set to “1”. The
contents of the register can also be read back by
the microcontroller.
Output Macrocells (OMCs)
The CPLD OMCs occupy a location in the
microcontroller’s
address
space.
The
microcontroller can read the output of the OMCs.
If the Mask Macrocell Register bits are not set,
writing to the Macrocell loads data to the Macrocell
flip flops. Refer to the section entitled “Output
Macrocell”, on page 29.
Mask Macrocell Register
Each Mask Register bit corresponds to an OMC
flip flop. When the Mask Register bit is set to a “1”,
loading data into the OMC flip flop is blocked. The
default value is “0” or unblocked.
Inpu t Macrocells (IMCs)
The IMCs can be used to latch or store external
inputs. The outputs of the IMCs are routed to the
PLD
input bus, and
can be
read by the
microcontroller. Refer to the section entitled
“PLDs”, on page 23.
Enable Out
The Enable Out register can be read by the
microcontroller. It contains the output enable
values for a given port. A “1” indicates the driver is
in output mode. A “0” indicates the driver is in tri-
state and the pin is in input mode.
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and
structure, as shown in Figure 29. The two ports
can be configured to perform one or more of the
following functions:
t MCU I/O Mode
t CPLD Output – Macrocells McellAB[7:0] can be
connected to Port A or Port B. McellBC[7:0] can be
connected to Port B or Port C.
t CPLD Input – Via the input Macrocells.
t Latched Address output – Provide latched
address output per Table 32.
t Address In – Additional high address inputs
using the Input Macrocells.
t Open Drain/Slew Rate – pins PA[3:0] and
PB[3:0] can be configured to fast slew rate, pins
PA[7:4] and PB[7:4] can be configured to Open
Drain Mode.
t Data Port – Port A to D[7:0] for 8 bit non-
multiplexed bus
t Multiplexed Address/Data port for certain types
of microcontroller interfaces.
Figu re 30. Port C Structure
Note: 1. ISP or Battery Back-up
INTERNAL
DATA
BUS
DATA OUT
REG.
DQ
WR
MCELLBC[ 7:0]
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD-INPUT
DIR REG.
INPUT
MACROCELL
ENABLE OUT
SPECIAL FUNCTION
1
SPECIAL FUNCTION
1
CONFIGURATION
BIT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT C PIN
DATA OUT
AI02888
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