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參數(shù)資料
| 型號： | M8813F3Y-90K1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 2/85頁 |
| 文件大小： | 601K |
| 代理商： | M8813F3Y-90K1T |
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M88 FAMILY
10/85
Note: 1. The pin numbers in this table are for the PLCC package only. See the package information, on page 79 onwards, for pin numbers
on other package types.
2. These functions can be multiplexed with other functions.
Table 8. I/O Port Latched Address Output Assignments1
Note: 1. Refer to the section entitled “I/O Ports”, on page 39, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
PC5
13
I/O
PC5 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellBC5) output.
3. Input to the PLDs.
4. TDI input2 for the JTAG interface.
This pin can be configured as a CMOS or Open Drain output.
PC6
12
I/O
PC6 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellBC6) output.
3. Input to the PLDs.
4. TDO output2 for the JTAG interface.
This pin can be configured as a CMOS or Open Drain output.
PC7
11
I/O
PC7 pin of Port C. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. CPLD Macrocell (McellBC7) output.
3. Input to the PLDs.
4. DBE — active-low Data Byte Enable input from 68HC912 type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0
10
I/O
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O — write or read from a standard output or input port.
3. Input to the PLDs.
4. CPLD output (external chip select).
PD1
9
I/O
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (external chip select).
4. CLKIN — clock input to the CPLD Macrocells, the automatic power-down unit’s power-
down counter, and the CPLD AND array.
PD2
8
I/O
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O — write to or read from a standard output or input port.
2. Input to the PLDs.
3. CPLD output (external chip select).
4. CSI — chip select input. When low, the MCU can access the PSD memory and I/O.
When high, the PSD memory blocks are disabled to conserve power.
VCC
15, 38
Power pins
GND
1, 16,
26
Ground pins
Microcontroller
Port A
Port B
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-bit)
N/A
Address [7:4]
Address [11:8]
N/A
80C251 (page mode)
N/A
Address [11:8]
Address [15:12]
All other 8-bit multiplexed
Address [3:0]
Address [7:4]
Address [3:0]
Address [7:4]
8-bit non-multiplexed bus
N/A
Address [3:0]
Address [7:4]
Pin Name
Pin1
Type
Description
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| M906-01-187.5000LF | 187.5 MHz, OTHER CLOCK GENERATOR, CQCC36 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M88141W-15K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-15K6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-15T1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-15T6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
| M88141W-90K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs |
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