參數(shù)資料
型號(hào): M8813F3Y-90K1T
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝: PLASTIC, LCC-52
文件頁(yè)數(shù): 37/85頁(yè)
文件大?。?/td> 601K
代理商: M8813F3Y-90K1T
M88 FAMILY
42/85
Figu re 28. Peripheral I/O Mode
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0 - PA7
D0 - D7
DATA BUS
AI02886
The PLD I/O Mode is specified in PSDabel by
declaring the port pins, and then writing an
equation assigning the PLD I/O to a port.
Address Out Mode
For microcontrollers with a multiplexed address/
data bus, Address Out Mode can be used to drive
latched addresses onto the port pins. These port
pins can, in turn, drive external devices. Either the
output enable or the corresponding bits of both the
Direction Register and Control Register must be
set to a ‘1’ for pins to use Address Out Mode. See
Table 24 for the address output pin assignments
on Ports A and B for various MCUs.
For non-multiplexed 8 bit bus mode, address lines
A[7:0] are available to Port B in Address Out
Mode.
Note: Do not drive address lines with Address Out
Mode to an external memory device if it is intended
for the MCU to boot from the external device. The
MCU must first boot from PSD memory so the
Direction and Control register bits can be set.
Address In Mode
For microcontrollers that have more than 16
address lines, the higher addresses can be
connected to Port A, B, C, and D. The address
input can be latched in the Input Macrocell by the
address strobe (ALE/AS). Any input that is
included in the DPLD equations for the PLD’s
Flash, EEPROM, or SRAM is considered to be an
address input.
Table 26. Port Pin Direction Control, Output Enable P.T. Not Defined
Table 27. Port Pin Direction Control, Output Enable P.T. Defined
Table 28. Port Direction Assignment Example
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Direction Register Bit
Outpu t Enable P.T.
Port Pin Mode
0
Input
0
1
Output
1
0
Output
1
Output
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
0
1
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