參數(shù)資料
型號(hào)： M8813F3Y-90K1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝： PLASTIC, LCC-52
文件頁(yè)數(shù)： 71/85頁(yè)
文件大小： 601K
代理商： M8813F3Y-90K1
73/85
M88 FAMILY
Table 53A. Port A Peripheral Data Mode Read Timing (5 V Range)
Table 53B. Port A Peripheral Data Mode Read Timing (3 V Range)
Table 54A. Port A Peripheral Data Mode Write Timing (5 V Range)
Note: 1. RD has the same timing as the DS, LDS, UDS, and PSEN signals.
2. WR has the same timing as the E, DS, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Symbol
Parameter
Condi tions
-90
-15
Turbo
Off
Unit
Min
Max
Min
Max
tAVQV (PA)
Address Valid to Data
Valid
(Note 3)
35
45
Add 10
ns
tSLQV (PA)
CSI Valid to Data Valid
35
45
Add 10
ns
tRLQV (PA)
RD to Data Valid
(Notes 1,4)
32
40
ns
RD to Data Valid 8031 Mode
38
45
ns
tDVQV (PA)
Data In to Data Out Valid
30
38
ns
tQXRH (PA)
RD Data Hold Time
0
ns
tRLRH (PA)
RD Pulse Width
(Note 1)
32
35
ns
tRHQZ (PA)
RD to Data High-Z
(Note 1)
25
33
ns
Symbol
Parameter
Condi tions
-15
Turbo
Off
Unit
Min
Max
tAVQV (PA)
Address Valid to Data Valid
(Note 3)
87
Add 20
ns
tSLQV (PA)
CSI Valid to Data Valid
(Notes 1,4)
70
Add 20
ns
RD to Data Valid
40
ns
tRLQV (PA)
RD to Data Valid 8031 Mode
45
ns
tDVQV (PA)
Data In to Data Out Valid
50
ns
tQXRH (PA)
RD Data Hold Time
0
ns
tRLRH (PA)
RD Pulse Width
(Note 1)
36
ns
tRHQZ (PA)
RD to Data High-Z
(Note 1)
32
ns
Symbol
Parameter
Condition s
-90
-15
Unit
Min
Max
Min
Max
tWLQV (PA)
WR to Data Propagation Delay
(Note 2)
35
40
ns
tDVQV (PA)
Data to Port A Data Propagation
Delay
(Note 5)
30
38
ns
tWHQZ (PA)
WR Invalid to Port A Tri-state
(Note 2)
25
33
ns
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