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參數(shù)資料
| 型號： | M8813F3Y-90K1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 46/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F3Y-90K1 |
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M88 FAMILY
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Table 34. Power Management Mode Registers PMMR21
Note: 1. The bits of this register are cleared to zero following power up. Subsequent reset pulses will not clear the registers.
Table 35. APD Counter Operation
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
PLD array
CNTL0
0 = on Cntl0 input to the PLD AND array is connected.
1 = off Cntl0 input to PLD AND array is disconnected, saving power.
Bit 3
PLD array
CNTL1
0 = on Cntl1 input to the PLD AND array is connected.
1 = off Cntl1 input to PLD AND array is disconnected, saving power.
Bit 4
PLD array
CNTL2
0 = on Cntl2 input to the PLD AND array is connected.
1 = off Cntl2 input to PLD AND array is disconnected, saving power.
Bit 5
PLD array
ALE
0 = on ALE input to the PLD AND array is connected.
1 = off ALE input to PLD AND array is disconnected, saving power.
Bit 6
PLD array
DBE
0 = on DBE input to the PLD AND array is connected.
1 = off DBE input to PLD AND array is disconnected, saving power.
Bit 7
X
0
Not used, and should be set to zero.
APD Enable Bit
ALE PD Polarity
ALE Level
APD Counter
0
X
Not Counting
1
X
Pulsing
Not Counting
1
Counting (Generates PDN after 15 Clocks)
1
0
Counting (Generates PDN after 15 Clocks)
Figu re 35. Reset Input Timing
t NLNH
t OPR
RESET
AI02893
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