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參數(shù)資料
| 型號(hào)： | M8813F3Y-90K1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 44/85頁 |
| 文件大?。?/td> | 601K |
| 代理商： | M8813F3Y-90K1 |
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49/85
M88 FAMILY
Figu re 34. Enable Power Down Flow Chart
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 2 through 6.
AI02892
Table 33. Power Management Mode Registers PMMR0
1
Note: 1. The bits of this register are cleared to zero following power up. Subsequent reset pulses will not clear the registers.
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
APD Enable
0 = off Automatic Power Down (APD) is disabled.
1 = on Automatic Power Down (APD) is enabled.
Bit 2
X
0
Not used, and should be set to zero.
Bit 3
PLD Turbo
0 = on PLD Turbo is on
1 = off PLD Turbo is off, saving power.
Bit 4
PLD Array clk
0= on
CLKIN input to the PLD AND array is connected. Every CLKIN change will power up
the PLD when Turbo bit is off.
1 = off CLKIN input to PLD AND array is disconnected, saving power.
Bit 5
PLD MCell clk
0 = on CLKIN input to the PLD Macrocells is connected.
1 = off CLKIN input to PLD Macrocells is disconnected, saving power.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
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| M8813F3Y-90T1 | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| M8803F3Y-90K1T | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
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