參數(shù)資料
型號(hào)： M8803F2W-15T1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： PLASTIC, QFP-52
文件頁數(shù)： 38/85頁
文件大小： 601K
代理商： M8803F2W-15T1
43/85
M88 FAMILY
Table 29. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port D
NA
Slew
Rate
Slew
Rate
Slew
Rate
Data Port Mode
Port A can be used as a data bus port for a
microcontroller with a non-multiplexed address/
data bus. The Data Port is connected to the data
bus of the microcontroller. The general I/O
functions are disabled in Port A if the port is
configured as a Data Port.
Peripheral I/O Mode
Peripheral I/O Mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-state, bi-directional data buffer for
the
microcontroller.
Peripheral
I/O
Mode
is
enabled by setting Bit 7 of the VM Register to a ‘1’.
Figure 28 shows how Port A acts as a bi-
directional buffer for the microcontroller data bus if
Peripheral I/O Mode is enabled. An equation for
PSEL0 and/or PSEL1 must be written in PSDabel.
The buffer is tri-stated when PSEL 0 or 1 is not
active.
JTAG ISP
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port C
because ISP is not performed during normal
system operation. For more information on the
JTAG
Port,
refer
to
the
section
entitled
“Programming
In-Circuit
using
the
JTAG
Interface”, on page 53.
Port Configu ration Registers (PCRs)
Each
port
has
a
set
of
PCRs
used
for
configuration. The contents of the registers can be
accessed by the microcontroller through normal
read/write bus cycles at the addresses given in
Table 9. The addresses in Table 9 are the offsets
in hex from the base of the CSIOP register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three PCRs, shown in Table 25, are used
for setting the port configurations. The default
power-up state for each register in Table 25 is 00h.
Control Register
Any bit set to ‘0’ in the Control Register sets the
corresponding Port pin to MCU I/O Mode, and a ‘1’
sets it to Address Out Mode. The default mode is
MCU I/O. Only Ports A and B have an associated
Control Register.
Table 30. Port Data Registers
Register Name
Port
MCU Access
Data In
A,B,C,D
Read – input on pin
Data Out
A,B,C,D
Write/Read
Output Macrocell
A,B,C
Read – outputs of Macrocells
Write – loading Macrocells Flip-Flop
Mask Macrocell
A,B,C
Write/Read – prevents loading into a given
Macrocell
Input Macrocell
A,B,C
Read – outputs of the Input Macrocells
Enable Out
A,B,C
Read – the output enable control of the port driver
相關(guān)PDF資料
PDF描述
M8813F3W-15K1 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
M8813F3Y-90K1 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
M8813F3Y-90T1 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
M8803F3Y-90K1T 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
M8813F3Y-90K1T 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M8805/100-007 制造商:OTTO Engineering Inc 功能描述:M8805/100-007
M8805/100-009 制造商:OTTO Engineering Inc 功能描述:M8805/100-009
M8805/100-010 制造商:OTTO Engineering Inc 功能描述:M8805/100-010
M8805/100-015 制造商:OTTO Engineering Inc 功能描述:M8805/100-015
M8805/100-016 制造商:OTTO Engineering Inc 功能描述:M8805/100-016
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*