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M88 FAMILY
product term of any of the array outputs are not
defined and that port pin is not defined as a CPLD
output in the PSDabel file, then the Direction
Register has sole control of the buffer that drives
the port pin.
The contents of these registers can be altered by
the microcontroller. The PDB feedback path
allows the microcontroller to check the contents of
the registers.
Ports
A, B,
and
C have embedded
Input
Macrocells (IMCs). The IMCs can be configured
as latches, registers, or direct inputs to the PLDs.
The latches and registers are clocked by the
address strobe (AS/ALE) or a product term from
the PLD AND array. The outputs from the IMCs
drive the PLD input bus and can be read by the
microcontroller. Refer to the section entitled “Input
Macrocells (IMCs)”, on page 33.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the microcontroller writing to the Control
Registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft
must be programmed into the device and cannot
be changed unless the device is reprogrammed.
The
modes
that can
be
changed
by
the
microcontroller can be done so dynamically at run-
time. The
PLD I/O, Data Port, Address Input, and Peripheral
I/O modes are the only modes that must be
defined before programming the device. All other
modes can be changed by the microcontroller at
run-time. See Application Note AN1171 for more
detail.
Table 22 summarizes which modes are available
on each port. Table 25 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the
M88x3Fxx FLASH+PSD ports to expand its own I/
O ports. By setting up the CSIOP space, the ports
on the M88x3Fxx FLASH+PSD are mapped into
the microcontroller address space. The addresses
of the ports are listed in Table 9.
A port pin can be put into MCU I/O mode by writing
a ‘0’ to the corresponding bit in the Control
Register. The MCU I/O direction may be changed
by writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See the section entitled “Direction Register”, on
page 44. When the pin is configured as an output,
the content of the Data Out Register drives the pin.
When configured as an input, the microcontroller
can read the port input through the Data In buffer.
See Figure 27.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equations are written for them in
PSDabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD’s Input Macrocells, and/or as an output from
the CPLD’s Output Macrocells. The output can be
tri-stated with a control signal. This output enable
control signal can be defined by a product term
from the PLD, or by setting the corresponding bit
in the Direction Register to ‘0’. The corresponding
bit in the Direction Register must not be set to ‘1’ if
the pin is defined as a PLD input pin in PSDabel.
Table 24. I/O Port Latched Address Output Assignments
Note: 1. N/A = Not Applicable.
Microcontroller
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-Bit)
N/A1
Address (7:4)
Address (11:8)
N/A
80C251
(Page Mode)
N/A
Address (11:8)
Address (15:12)
All Other
8-Bit Multiplexed
Address (3:0)
Address (7:4)
Address (3:0)
Address (7:4)
8-Bit
Non-Multiplexed Bus
N/A
Address [3:0]
Address [7:4]
Table 25. Port Configuration Registers
Note: 1. See Table 29 for Drive Register bit definition.
Register Name
Port
MCU Access
Control
A,B
Write/Read
Direction
A,B,C,D
Write/Read
Drive Select1
A,B,C,D
Write/Read