參數(shù)資料
型號： M7A3PE600-FPQ208I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PQFP208
封裝： 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù)： 82/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
2- 8
A dvanced v0. 5
Clock Resources (VersaNets)
ProASIC3E devices offer powerful and flexible control of
circuit timing through the use of analog circuitry. Each
chip has six CCCs containing a phase-locked loop (PLL)
core, delay lines, a phase shifter (0°, 90°, 180°, 270°),
clock multipliers/dividers, and all the circuitry needed for
the selection and interconnection of inputs to the
VersaNet global network. The east and west CCCs each
have access to three VersaNet global lines on each side of
the chip (six total lines). The CCCs at the four corners
each have access to three quadrant global lines in each
quadrant of the chip.
Advantages of the VersaNet Approach
One of the architectural benefits of ProASIC3E is the set of
powerful
and
low-delay
VersaNet
global
networks.
ProASIC3E offers six chip (main) global networks that are
distributed from the center of the FPGA array (Figure 2-8).
In addition, ProASIC3E devices have three regional globals
in each of the four chip quadrants. Each core VersaTile has
access to nine global network resources: three quadrant
and six chip (main) global networks, and a total of 18
globals on the device. Each of these networks contains
spines and ribs that reach all the VersaTiles in the quadrants
(Figure 2-9 on page 2-9). This flexible VersaNet global
network architecture allows users to map up to 252
different internal/external clocks in a ProASIC3E device.
Details on the VersaNet networks are given in Table 2-2 on
page 2-9. The flexible use of the ProASIC3E VersaNet global
network allows the designer to address several design
requirements. User applications that are clock-resource-
intensive can easily route external or gated internal clocks
using VersaNet global routing networks. Designers can also
drastically reduce delay penalties and minimize resource
usage by mapping critical, high-fanout nets to the VersaNet
global network.
Figure 2-8 Overview of ProASIC3E VersaNet Global Network
Quadrant Global Pads
Top Spine
Bottom Spine
Pad Ring
Pad
Ring
I/O
Ring
I/O
Ring
Chip (main)
Global Pads
Spine-Selection
Tree MUX
Global
Pads
High-Performance
VersaNet Global Network
Main (chip)
Global Network
Global Spine
Global Ribs
相關(guān)PDF資料
PDF描述
M7A3PE600-FPQG208I FPGA, 600000 GATES, PQFP208
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