參數(shù)資料
型號(hào): M7A3PE600-FPQ208I
元件分類: FPGA
英文描述: FPGA, 600000 GATES, PQFP208
封裝: 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù): 75/168頁
文件大小: 1335K
代理商: M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
5- 2
A dvanced v0. 5
Advanced v0.3
continued
The "I/O User Input/Output" pin description was updated to include information on what
happens when the pin is unused.
The "JTAG Pins" description was updated to include information on what happens when the
pin is unused.
The "Programming" section was updated to include information concerning serialization.
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD information.
The "DC and Switching Characteristics" section chapter was updated with new information.
starting on
page 3-1
The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 2-4.
EXTFB was removed from Figure 2-18.
The LVPECL specification in Table 2-16 was updated.
Table 2-17 was updated.
The "Cold-Sparing Support" was updated.
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
The "JTAG Pins" was updated.
Table 3-6 was updated.
PAC4 was updated in Table 3-10.
Table 3-17 was updated.
The note in Table 3-24 was updated.
All Timing Characteristic tables were updated from LVTTL to Register Delays.
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
FTCKMAX was updated in Table 3-98.
Advanced v0.2
The "I/Os Per Package1" table was updated.
Figure 2-4 was updated.
The "PLL Macro" section was updated.
Figure 2-16 was updated.
Figure 2-19 was updated.
Table 2-6 was updated.
Table 2-7 was updated.
The Table 2-14 was updated.
Figure 2-23 was updated.
Table 2-18 was updated.
Table 2-20 was updated.
Previous Version
Changes in Current Version (Advanced v0.5)
Page
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