參數(shù)資料
型號: M7A3PE600-FPQ208I
元件分類: FPGA
英文描述: FPGA, 600000 GATES, PQFP208
封裝: 0.50 MM PITCH, PLASTIC, QFP-208
文件頁數(shù): 133/168頁
文件大?。?/td> 1335K
代理商: M7A3PE600-FPQ208I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-55
The serial pins are used to serially connect all the boundary scan register cells in a device into a boundary scan register
chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic I/O
tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or
observe the logic state of each I/O.
Figure 2-37 Boundary Scan Chain in ProASIC3E
Table 2-25 Boundary Scan Opcodes
Hex Opcode
EXTEST
00
HIGHZ
07
USERCODE
0E
SAMPLE/PRELOAD
01
IDCODE
0F
CLAMP
05
BYPASS
FF
Device
Logic
TDI
TCK
TMS
TRST
TDO
I/O
Bypass Register
Instruction
Register
TAP
Controller
Test Data
Registers
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