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參數(shù)資料
| 型號(hào)： | M7A3PE600-FFGG484I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 600000 GATES, PBGA484 |
| 封裝： | 1 MM PITCH, GREEN, FBGA-484 |
| 文件頁數(shù)： | 84/168頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | M7A3PE600-FFGG484I |
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ProASIC3E Flash Family FPGAs
2- 10
Advanced v0.5
VersaNet Global Networks and Spine Access
The ProASIC3E architecture contains a total of 18
segmented
global
networks
that
can
access
the
VersaTiles, SRAM memory, and I/O tiles of the ProASIC3E
device. There are nine global network resources in each
device quadrant: three quadrant globals and six chip
(main) global networks. Each device has a total of 18
globals. These VersaNet global networks offer fast, low-
skew routing resources for high-fanout nets, including
clock signals. In addition, these highly segmented global
networks offer users the flexibility to create low-skew
local networks using spines for up to 252 internal/
external clocks (in an A3PE3000 device) or other high-
fanout nets in ProASIC3E devices. Optimal usage of these
low-skew networks can result in significant improvement
in design performance on ProASIC3E devices.
The nine spines available in a vertical column reside in
global networks with two separate regions of scope: the
quadrant global network, which has three spines, and
the chip (main) global network, which has six spines.
Note that there are three quadrant spines in each
quadrant of the device. There are four quadrant global
network regions per device (Figure 2-9 on page 2-9).
The spines are the vertical branches of the global
network tree, shown in Figure 2-10 on page 2-11. Each
spine in a vertical column of a chip (main) global
network is further divided into two equal-length spine
segments: one in the top and one in the bottom half of
the die.
Each spine and its associated ribs cover a certain area of
the ProASIC3E device (the "scope" of the spine; see
Figure 2-8 on page 2-8). Each spine is accessed by the
dedicated global network MUX tree architecture, which
defines how a particular spine is driven—either by the
signal on the global network from a CCC, for example, or
by another net defined by the user (Figure 2-11 on page
2-12). Quadrant spines can be driven from user I/Os on
the north and south sides of the die. The ability to drive
spines in the quadrant global networks can have a
significant effect on system performance for high-fanout
inputs to a design.
Details of the chip (main) global network spine-selection
MUX are presented in Figure 2-11 on page 2-12. The
spine drivers for each spine are located in the middle of
the die.
Quadrant spines are driven from a north or south rib.
Access to the top and bottom ribs is from the corner CCC
or from the I/Os on the north and south sides of the
device.
For details on using spines in ProASIC3E devices, see the
Actel application note Using Global Resources in Actel
相關(guān)PDF資料 |
PDF描述 |
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| M7A3PE600-FPQG208I | FPGA, 600000 GATES, PQFP208 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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