參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 166/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-29
1.8 V LVCMOS
Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.8 V
applications. It uses 1.8 V input buffer and push-pull output buffer.
Table 3-33 Minimum and Maximum DC Input and Output Levels
1.8 V LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V
Max, V
Min, V
Max, V Max, V
Min, V
mA
Max, mA1 Max, mA1
A2 A2
2 mA
–0.3
0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
2
11
9
10
4 mA
–0.3
0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
4
22
17
10
6 mA
–0.3
0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
6
44
35
10
8 mA
–0.3
0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
8
51
45
10
12 mA
–0.3
0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
12
74
91
10
16 mA
–0.3
0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
16
74
91
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Figure 3-8
AC Loading
Table 3-34 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
CLOAD (pF)
0
1.8
0.9
–
35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Test Point
Enable Path
Datapath
R to V
for t /t /t
CCI
LZ ZL
ZLS
35 pF for t
/t
/t /t
ZH ZHS
ZLS
ZL
5 pF for t
/t
HZ
LZ
R to GND for t
/t
HZ
ZH
ZHS
35 pF
R = 1 k
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