參數(shù)資料
型號(hào): M7A3PE600-FFGG484I
元件分類: FPGA
英文描述: FPGA, 600000 GATES, PBGA484
封裝: 1 MM PITCH, GREEN, FBGA-484
文件頁(yè)數(shù): 19/168頁(yè)
文件大?。?/td> 1335K
代理商: M7A3PE600-FFGG484I
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ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-47
Timing Characteristics
BLVDS/M-LVDS
Bus
LVDS
(BLVDS)
and
Multipoint
LVDS
(M-LVDS)
specifications extend the existing LVDS standard to high-
performance multipoint bus applications. Multidrop and
multipoint
bus
configurations
may
contain
any
combination of drivers, receivers and transceivers. Actel
LVDS drivers provide the higher drive current required by
BLVDS and M-LVDS to accommodate the loading. The
driver requires series terminations for better signal quality
and to control voltage swing. Termination is also required
at both ends of the bus since the driver can be located
anywhere on the bus. These configurations can be
implemented using TRIBUF_LVDS and BIBUF_LVDS macros
along with appropriate terminations. Multipoint designs
using Actel LVDS macros can achieve upto 200 MHz with a
maximum of 20 loads. A sample application is given in
Figure 3-22. The input and output buffer delays are
available in the LVDS section in Table 3-76.
Example: For a bus consisting of 20 equidistant loads, the
following terminations provide the required differential
voltage, in worst case Industrial operating conditions, at
the farthest receiver: RS =60 and RT =70 , given
Z0 =50 (2") and a Zstub =50 (~1.5").
Table 3-76 LVDS
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
–F
0.79
2.25
0.05
2.18
ns
Std.
0.66
1.87
0.04
1.82
ns
–1
0.56
1.59
0.04
1.55
ns
–2
0.49
1.40
0.03
1.36
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Figure 3-22 BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
...
R
T
R
T
BIBUF_LVDS
R
+
-
T
+
-
R
+
-
T
+
-
D
+
-
EN
Receiver
Transceiver
Receiver
Transceiver
Driver
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
stub
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
Z
0
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