參數(shù)資料
型號(hào)： M6MGT166S4BWG
廠商： Mitsubishi Electric Corporation
英文描述： Series RC1083 rocker switches rated to 15 amp and snap-in panel mount
中文描述： 3.3的CMOS只快閃記憶體
文件頁數(shù)： 26/30頁
文件大?。?/td> 259K
代理商： M6MGT166S4BWG
Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
M6MGB/T166S4BWG
26
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
(S-Vcc=2.7 ~ 3.6V, unless otherwise noted)
Input rise time and fall time
Reference level
Output loads
2.7V~3.6V
V
IH
=2.4V, V
IL
=0.4V
5ns
V
OH
=V
OL
=1.5V
Transition is measured 500mV from
steady state voltage.(for t
en
,t
dis
)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Supply voltage
Input pulse
1TTL
CL
DQ
Fig.1 Output load
Including scope and
jig capacitance
(3) WRITE CYCLE
t
su
(A-WH)
t
su
(LB)
t
su
(UB)
t
CW
t
w
(W)
t
su
(A)
t
su
(CE1)
t
su
(CE2)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
Chip select 1 setup time
Chip select 2 setup time
ns
ns
ns
ns
ns
ns
ns
ns
85
60
0
70
70
70
70
70
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Limits
SRAM
Units
Max
Min
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to S-WE#
Lower Byte control setup time
Upper Byte control setup time
Data setup time
Data hold time
Write recovery time
Output disable time from S-WE# low
Output disable time from S-OE# high
Output enable time from S-WE# high
Output enable time from S-OE# low
30
30
5
5
35
0
0
(2) READ CYCLE
Output disable time after S-CE1# high
Output disable time after S-CE2 low
t
CR
t
a
(A)
ns
ns
ns
ns
t
a
(CE1)
t
a
(CE2)
t
a
(OE)
t
dis
(CE1)
t
dis
(CE2)
t
dis
(OE)
t
en
(CE1)
t
en
(CE2)
t
en
(OE)
t
V
(A)
85
10
10
45
30
30
SRAM
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Limits
Units
Max
Min
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Data valid time after address
t
a
(LB)
t
a
(UB)
Lower Byte control access time
Upper Byte control access time
t
dis
(LB)
t
dis
(UB)
Output disable time after S-LB# high
Output disable time after S-UB# high
Output disable time after S-OE high
Output enable time after S-CE1# low
Output enable time after S-CE2 high
t
dis
(LB)
t
dis
(UB)
Output enable time after S-LB# low
Output enable time after S-UB# low
Output enable time after S-OE low
ns
ns
ns
ns
85
85
85
85
85
30
30
30
10
10
5
10
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