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參數(shù)資料
| 型號： | M5M28F101AFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY |
| 中文描述： | 1048576位（131072 - Word的8位）的CMOS閃存 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 96K |
| 代理商： | M5M28F101AFP |
MITSUBISHI LSIs
1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY
M5M28F101AFP,J,VP,RV-85,-10
(970407)
2
1.
2.
3.
FUNCTION
M5M28F101A are set to the Read-only mode or Read-write mode
by applying the voltage of V
PPL
or V
PPH
, respectively, to V
PP
pin. In
Read-only mode, three operation modes, Read, Out-put disable
and Stand-by are accessible. While, in Read-Write mode, four
operation modes, Read, Output disable, Stand-by and Write are
functional.
BLOCK DIAGRAM
DATA PROTECTION
Power Supply Voltage
When the power supply voltage (Vcc) is less than 2.5V, the
device ignores WE signal.
Write Inhibit
In the cases, as below, write mode is not set.
1) When OE is terminated to the low level.
2) From each mode beginning through finish after 2nd rising
edge of WE for program, auto-program, erase, and auto-
erase.
Over-erase Protection
Just after powering up, if erase command is inputted, erase
operation is not executed. Once byte-program is performed or
verified data is not FFH in the erase-verify mode, successive
command input for erase will be accepted. Because of this, it
is applicable to the case of multi-chip erasing simultaneously.
PROGRAM
VOLTAGE SW.
X-DECODER
Y-DECODER
CHIP ENABLE
OUTPUT ENABLE
CIRCUITS
ERASE VOLTAGE SW.
131072 WORD
x8 BIT
CELL MATRIX
Y-GATE
OUTPUT SENSE
AND
OUTPUT BUFFERS
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
16
A
15
A
14
A
13
A
12
A
11
A
10
VERIFY
VOLTAGE
SW.
TIMER
CONTROL
CIRCUITS
COMMAND
LATCH
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CE
OE
WE
V
PP
(5V, 12V)
V
CC
(5V)
GND (0V)
ADDRESS
INPUTS
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WRITE ENABLE
INPUT
DATA INPUTS/OUTPUTS
Read
Set CE and OE terminals to the read mode (low level). Low level
input to CE and OE, and address signals to the address inputs
(A
0~
A
16
) make the data contents of the designated address
location available at data input/output(D
0~
D
7
).
Output Disable
When OE is at high level, output from the devices is disabled. Data
input/output are in a high-impedance (High-Z) state.
Stand-by
When CE is at high level, the devices is in the stand-by mode and
its power consumption is substantially reduced. Data input/output
are in a high-impedance (High-Z) state.
Write
Software command accomplishes program and erase operations
via the command latch in the device, when high voltage is supplied
to V
PP
. The contents of the latch serve as input to the internal
controller. The controller output dictates the function of device. The
command latch is written by bringing WE to low level, while CE is
at low level and OE is at high level. Addresses are latched on the
falling edge of WE, while data is latched on the rising edge of WE.
Standard micro-processor write timings are used.
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| M5M28F101J12 | 制造商:MITS 功能描述:28F010-120 S8H2A |
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| M5M29FB800FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:8,388,608-BIT (1048,576-576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY |
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