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參數(shù)資料
| 型號(hào)： | M54HC393D |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 計(jì)數(shù)器 |
| 英文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 333K |
| 代理商： | M54HC393D |
1/12
May 2004
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HIGH SPEED:
fMAX =79MHz (TYP.) at VCC =6V
s
LOW POWER DISSIPATION:
ICC =4A(MAX.) at TA=25°C
s
HIGH NOISE IMMUNITY:
VNIH =VNIL = 28% VCC (MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL =4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH tPHL
s
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 393
s
SPACE GRADE-1: ESA SCC QUALIFIED
s
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s
DEVICE FULLY COMPLIANT WITH
SCC-9204-074
DESCRIPTION
The M54HC393 is an high speed CMOS DUAL
BINARY COUNTER fabricated with silicon gate
C2MOS technology.
This counter circuit contains independent ripple
carry counters and two 4-bit ripple carry binary
counters, which can be cascaded to create a
single divide by 256 counter.
Each 4-bit counter is increases during the high to
low transition (negative edge) of the clock input,
and each has an independent clear input. When
CLEAR is set to low, all four bits of each counter
are set to a low level. This enables count
truncation and allows the implementation of divide
by N counter configurations.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M54HC393
RAD-HARD DUAL BINARY COUNTER
PIN CONNECTION
ORDER CODES
PACKAGE
FM
EM
DILC
M54HC14D
M54HC14D1
FPC
M54HC14K
M54HC14K1
DILC-14
FPC-14
Rev. 1
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