參數(shù)資料
型號(hào): M41ST87YWX6
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.300 INCH, PLASTIC, SO-28
文件頁(yè)數(shù): 4/38頁(yè)
文件大?。?/td> 569K
代理商: M41ST87YWX6
M41ST87Y, M41ST87W
12/38
Figure 9. WRITE Cycle Timing: RTC & External SRAM Control Signals
Figure 10. Bus Timing Requirements Sequence
Table 6. AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
Symbol
Parameter(1)
Min
Max
Unit
fSCL
SCL Clock Frequency
0
400
kHz
tBUF
Time the bus must be free before a new transmission can start
1.3
s
tEXPD
EX to ECON Propagation Delay
M41ST87Y
10
ns
M41ST87W
15
ns
tF
SDA and SCL Fall Time
300
ns
tHD:DAT
(2)
Data Hold Time
0
s
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
s
tR
SDA and SCL Rise Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
AI03663
EX
ECON
tEXPD
AI00589
SDA
P
tSU:STO
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STA
tBUF
S
P
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